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研究生: 莊賀凱
Juang, He-Kai
論文名稱: 垂直型態穿隧場效電晶體的製程及分析
Fabrication and Analysis of Silicon-Based Vertical-Type Tunneling Field-Effect Transistor
指導教授: 莊紹勳
Chung, Shao-Shiun
李敏鴻
Lee, Ming-Hung
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 中文
論文頁數: 61
中文關鍵詞: 穿隧場效電晶體垂直穿隧機制矽製程
英文關鍵詞: Tunnel FET, vertical tunneling mechanism, silicon-based
論文種類: 學術論文
相關次數: 點閱:113下載:0
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  • 應用穿隧機制的電晶體是近期頗被看好的新一代元件,與傳統的金氧半場效電晶體相比Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET),穿隧電晶體(Tunnel FET, TFET)具有以下幾個優點:(1)p-i-n的摻雜設計使得其漏電可有效被抑制,使得TFET相當適合作為低功率元件(2)發生能帶穿隧的區間大約只有10nm,這意謂TFET有著通道可被微縮到20nm以下的潛力(3)元件導通是依賴穿隧機制,因此可以超越MOSFET次臨界擺幅在60mV/dec的物理極限(4)TFET的臨界電壓VT是取決於能帶彎曲到出現穿隧效應時的偏壓點,隨著元件尺寸縮小,其VT roll-off現象不會像MOSFET這麼嚴重;目前研究的文獻均指出,TFET發展不如預期的最大因素就在於其導通電流難以做到跟MOSFET等元件相比,因此,就更需要找到一些方式來提升TFET的電流,本論文是利用垂直方向穿隧的機制來設計元件,藉此增加整個穿隧機制所產生的電流,提升TFET的導通電流,研究結果顯示,從導通電流的兩段上升可找到垂直穿隧電流的產生,且大面積的垂直穿隧確實能幫助TFET的導通電流提高,而源極摻雜保持在1x1019~1020cm-3會是較好的選擇,同時我們也利用模擬軟體來驗證實作元件的製程問題,發現在本論文的元件製作上,閘極氧化層是影響元件電性最主要的因素。

    Recently, a transistor with tunneling mechanism called Tunnel FET was proposed as the candidate of MOSFET. Compared to MOSFET, TFET has several advantages: (1)TFET is suitable for low power device due to the higher barrier of the reversed p-i-n junction in TFET. (2)The band-to-band tunneling region is about 10nm, so that the transistor can be shrunk down to 20nm gate length. (3)The subthreshold swing of TFET has ability to surmount 60mV/dec of MOSFET’s physical limit by its distinct working principle. (4)The threshold voltage of TFET depends on bending in the small region, but not in the whole channel region, Vt roll-off is much smaller than that of MOSFET while scaling. The major challenge of TFET is the boosting of on current. In this paper, we design a device with vertical tunneling structure for investigating how to enhance the on current of TFET. The analytic results show that we can find two parts of boosting current, the second boosting current is caused by vertical tunneling, we have proved it by band gap diagram of simulation. And the best source concentration is about 1x1019~1x1020cm-3. It can be adjusted to have appropriate threshold voltage and better subthreshold swing in this region. At the same time, we investigate the issue of fabrication by simulation. It shows that the major issue affecting our performance of device is the quality of gate oxide.The bad gate oxide induces trap assist tunneling, then the current of gate will directly tunnel through the gate oxide, and that’s where the leakage current come from.

    目錄 Abstract………………………………………………………………………I 中文摘要………………………………………………………………………II 誌謝…………………………………………………………………………….III 目錄…………………………………………………………………………….IV 圖目錄………………………………………………………………………VI 表目錄………………………………………………………………………….IX 第一章 緒論 1-1 電晶體操作機制……………………………………………………………2 1-2 電晶體材料…………………………………………………………………4 1-3 電晶體結構…………………………………………………………………5 第二章 穿隧型場效電晶體 2-1穿隧型場效電晶體的介紹.……….…………………………………...……7 2-2穿隧型場效電晶體的操作原理……………………………………….……7 第三章 實驗機台與製程介紹 3-1 製程機台介紹…..…………………………………………………………13 3-2 量測機台介紹………..……………………………………………………22 3-3 製程流程介紹……....……..………………………………………………23 3-3-1製程流程…………………………………………………………….23 3-3-2元件TEM圖………………………………………………...……….33 第四章 垂直型態穿隧場效電晶體的模擬 4-1 實驗動機…………………………………………………………………37 4-2 模擬結果分析……………………………………………………………37 4-2-1本質區的長度變化對元件特性影響……………………………….39 4-2-2閘極的延伸位置對元件特性影響…………………………………41 4-2-3環形佈植對元件特性影響…………………………………………43 4-2-4源極參雜濃度對元件特性影響……………………………………44 第五章 垂直型態穿隧場效電晶體的量測與分析比較 5-1 量測結果…………………………………………………………………48 5-1 實作與模擬比較………………………………………………………52 第六章 結論 6-1 垂直型態穿隧場效電晶體特性…………………………………………..57 參考文獻……………………………………………………………………58

    [1] F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus, “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance, ” in IEDM Tech. Dig., pp. 163-166, 2008.
    [2] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope, ” in IEDM Tech. Dig., pp. 947-949, 2008.
    [3] C. Hu, “Green Transistor as a Solution to the IC PowerCrisis, ” ICSICT, pp. 16-20 (2008).
    [4] A. Bowonder, P. Patel, K. Jeon, J. Oh, P. Majhi, H.-H. Tseng, and C. Hu, “Low-Voltage Green Transistor Using Ultra Shallow Junction and Hetero-Tunneling, ” IWJT, pp. 93-96 (2008).
    [5] C. Hu, D. Chou, P. Patel, and A. Bowonder, “Green Transistor -A VDD Scaling Path for Future Low Power ICs, ” VLSI-TSA, pp. 14-15, 2008.
    [6] A. Bowonder, P. Patel, K. Jeon, J. Oh, P. Majhi, H.-H. Tseng, and C. Hu, “Low-Voltage Green Transistor Using Hetero-Tunneling, ” SNW, p. 1, 2008.
    [7] C. Hu, “Reduce IC Power Consumption by >10x with a Green Transistor?, ”DRC, pp. 9-10, 2009.
    [8] C. Hu, P. Patel, A. Bowonder, K. Jeon, S. H. Kim, W. Y. Loh, C. Y. Kang, J. Oh, P. Majhi, A. Javey, T.-J. K. Liu, and R. Jammy, “Prospect of Tunneling Green Transistor for 0.1V CMOS, ” in IEDM Tech. Dig., pp. 387-390, 2010
    [9] T. Krishnamohan, D. Kim, T. Viet Dinh, A. Pham, B. Meinerzhagen, C. Jungemann, and K. Saraswat, “Comparison of (001), (110) and (111) Uniaxial- and Biaxial- Strained-Ge and Strained-Si PMOS DGFETs for All Channel orientations: Mobility Enhancement, Drive Current, Delay and Off-State Leakage, ” in IEDM Tech. Dig., pp. 947-950, 2008.
    [10] K. K. Bhuwalka, J. Schulze, and I. Eisele, “Performance Enahncement of Vertical Tunnel Field-Effect Transistor with SiGe in the p+ Layer, ” Japn. J. of Appl. Phys., vol. 43, no. 7A, pp. 4073-4078, 2004.
    [11] O. M. Nayfeh, C. N. Chleirigh, J. L. Hoyt, and D. A. Antoniadis, “Measurement of Enhanced Gate-Controlled Band-to-Band Tunneling in Highly Strained Silicon-Germanium Diodes, ” IEEE Electron Device Letter, vol. 29, no. 5, pp. 468-470, 2008.
    [12] C.-Y. Peng, F. Yuan, C.-Y. Yu, P.-S. Kuo, M. H. Lee, S. Maikap, C.-H. Hsu, and C. W. Liu, “Hole mobility enhancement of Si0.2Ge0.8 quantum well channel on Si,” Appl. Phys Lett., vol. 90, 012114, 2007.
    [13] S. Maikap, M. H. Lee, S. T. Chang, and C. W. Liu, “Characteristics of strained-germanium p- and n-channel field effect transistors on Si (111) substrate,” Semicond. Sci. Technol., vol. 22, pp. 342-347, 2007.
    [14] M. H. Lee, S. T. Chang, S. Maikap, C.-Y. Peng, and C.-H Lee, “High Ge Content of SiGe Channel p-MOSFETs on Si (110) Surfaces, ” IEEE Electron Device Lett., vol. 31, no. 2, pp. 141- 143, 2010.
    [15] M. H. Lee, S. T. Chang, T.-H. Wu, and W.-N. Tseng, “Driving Current Enhancement of Strained Ge (110) p-type Tunnel FETs and Anisotropic Effect, ” IEEE Electron Device Letter, vol. 32, no. 10, pp. 1355-1357, 2011.
    [16] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-Source Tunnel Field Effect Transistors with Record High ION/IOFF, ” in VLSI Symp. Tech. Dig., pp. 178-179, 2009.
    [17] K. Joen, W.-Y. Lop, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. King Liu, and C. Hu, “Si Tunnel Transistors with a Novel Silicided Source and 46mV/dec Swing, ” in VLSI Symp. Tech. Dig., pp. 121-122, 2010.
    [18] W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park, “70-nm Impact-Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs), ” in IEDM Tech. Dig., pp. 955-958, 2005.
    [19] A. Villalon, C. Le Royer, M. Casse, D. Cooper, B. Previtali, C. Tabone, J.-M. Hartmann, P. Perreau, P. Rivallin, J.-F. Damlencourt, F. Allain, F. Andrieu, O. Weber, O. Faynot, and T. Poiroux, “Strained Tunnel FETs with record ION: First Demonstration of ETSOI TFETs with SiGe channel and RSD, ” in VLSI Symp. Tech. Dig., pp. 49-50, 2012.
    [20] S. M. Sze, Physics of semiconductor devices, 2nd edition, John Wiley & Sons, Inc., 1981.
    [21] J. Moll, “Physics of Semiconductors” McGraw-Hill, New York, p. 253, 1964.
    [22] A. Seabaugh, “Tunnel Field-Effect Transistor – Engineer a Better Switch, ” IEEE IEDM short course, Dec. 4, 2011.

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