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研究生： 黃維熙
Huang, Wei-Hsi
論文名稱： 以Chipyard為基礎的SoC設計平台FPGA實現之研究
Research on FPGA Implementation of Chipyard-based SoC Design Platform
指導教授： 黃文吉
Hwang, Wen-Jyi
口試委員： 鮑興國
Pao, Hsing-Kuo
葉佐任
Yeh, Tso-Zen
黃文吉
Hwang, Wen-Jyi
口試日期： 2022/07/27
學位類別： 碩士
Master
系所名稱： 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年： 2022
畢業學年度： 110
語文別： 中文
論文頁數： 55
英文關鍵詞： FPGA, SoC, Chipyard
研究方法: 實驗設計法
DOI URL： http://doi.org/10.6345/NTNU202201330
論文種類： 學術論文
相關次數： 點閱：183  下載：54 
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    • 近年來在軟體上的AI加速器發展越來越多元化，並且在硬體上也有一些的發展及實現，而硬體AI加速器的優勢在於對特定資料格式做運算可以大幅提升速度，僅需使用資料流的方式就可以實現。
    本論文針對柏克萊大學提出的硬體開源框架Chipyard，提出一個硬體建構的流程，將RISC-V為基礎的CPU搭配AI硬體加速器整合於FPGA平台，並且完善RISC-V軟體開機流程，讓我們可以通過硬體建構流程調整所需的硬體資源，做出客製化的硬體電路，快速的去對CPU及AI硬體加速器於FPGA開發板上做有效的效能評估。

    致謝 i 摘要 ii 目錄 iii 表目錄 iv 圖目錄 v 第1章 緒論 1 1-1 研究背景 1 1-1-1 Chipyard 1 1-1-2 Existing SoC Design Platforms 3 1-2 研究動機 4 1-3 研究困難 5 1-4 研究目的 5 1-5 研究貢獻 6 第2章 理論基礎與背景 7 2-1 Chipyard Design Flow 7 2-2 Chisel 9 2-3 FIRRTL 10 2-4 Rocket Chip Generator 11 2-5 Rocket Core 13 2-6 Gemmini 加速器 14 第3章 研究方法 15 3-1 Hardware Design Flow 15 3-2 Software Building Flow 28 第4章 實驗數據與效能分析 34 4-1 實驗環境介紹 34 4-2 實驗設計 36 4-3 實驗效能評估 39 4-4 實驗結果 40 第5章 結論 46 參考文獻 47 附錄 52 附錄一 Rocket Chip chiptop 52 附錄二 編譯U-Boot及Linux Kernel 54 附錄三 SD卡燒錄 55

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