基於物理限制的原因，金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET)的次臨界擺幅無法低於60 mV/decade，使操作電壓Vdd無法持續往下微縮。穿隧型場效電晶(Tunnel Field Effect Transistor, TFET)近期受到許多研究團隊關注，由於不用同於金氧半場效電晶體操作機制，它是利用能帶至能帶的穿隧(Band-to-Band Tunneling)，因此能夠擁有低於60 mV/decade的次臨界擺幅，有利於操作電壓Vdd的微縮。
在本論文的研究，我們提出最大電場與最大能帶至能帶穿隧機率有相當的關聯性，以促使穿隧型場效電晶體元件性能進一步提升，利用半導體模擬工具 (Technology Computer Aided Design, TCAD)來應證。本文成功設計出穿隧電晶體由pTFET為矽鍺與矽、nTFET為砷化銦與銻化鎵所組成的互補式架構，且元件結構能使最大電場與最大能帶至能帶穿隧機率對齊，使穿隧機率大幅提升。模擬結果顯示在閘極形成一個鈍角的結構並搭配異質接面的方式，能使得元件相較於平面能有4個數量級的驅動電流值提升。最後，本研究的互補式傾斜閘極穿隧電晶體元件在適當角度的閘極結構下，能取代互補式金屬氧化半導體元件在低操作功率(Low Operation Power, LOP)及低待機功率(Low Standby Power, LSTP)操作狀態下的元件。

Due to the physical limitation, the sub-threshold swing (S.S.) of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) can not be below 60 mV/decade, which limits the scaling of the operation voltage (Vdd). Tunneling FETs (TFETs) have been attracted much more attention because Zener band-to-band tunneling (B2BT) allows S.S. smaller than 60 mV/decade, and hence Vdd can be accordingly scaled down.
In this research, we have proposed a new engineering concept for alignment between the maximum band-to-band tunneling rate and electric field that was designed to enhance the performance of TFETs, which has been demonstrated by Technology Computer Aided Design (TCAD). The structures of hetero junctions for pTFETs and nTFETs are SiGe/Si and InAs/GaSb, respectively. A novel structure of Tilt-Gate TFET has been introduced to increase the B2B tunneling probability by the exact alignment between maximum electric field and maximum B2BT rate. It was found that if the gate of TFET is formed an obtuse shape, the on-current can be dramatically improved by 4 orders in comparison with the planar transistors. Therefore, Tilt complementary TFET has been constructed and with its potential to replace the CMOS devices in LOP and LSTP applications by suitable design of the gate structure in the new design.

[1]S.Y. Wu, C. Y. Lin and M. C. Chiang, “A 16nm FinFET CMOS Technology for Mobile SoC and Computing Applications,” Electron Devices Meeting, pp. 224-227, 2013.
[2]C. Auth, “22 nm Fully-depleted Tri-gate CMOS Transistors,” CICC, pp. 1-6, 2012.
[3]K. Henson, H. Bu, M. H. Na and Y. Liang, “Gate Length Scaling and High Drive Currents Enabled for High Performance SOI Technology Using High-κ/Metal Gate,” Electron Devices Meeting, pp. 645-648, 2008.
[4]T. Y. Hsieh, “Self-Aligned Patterning with Implantation,” U.S. Patent, pp. 645-648, 2014.
[5]K. Mistry, “Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology,” Symposium on VLSI Technology, pp. 50-51, 2004.
[6]S. Amour, “An Advanced Low Power High Performance Strained Channel 65nm Technology,” IEEE International Electron Devices Meeting, pp. 1070-1071, 2005.
[7]C. Auth, A. Cappellani, J. S. H. Chun and A. Dalis, “45 nm high-κ/metal Gate Strain-enhanced Transistors,” VLSI Technology, pp. 128-129, 2008.
[8]P. Packan, S. Akbar, M. Amstrong and D. Bergstrom, “High Performance 32nm Logic Technology Featuring 2nd Generation High-κ/Metal Gate Transistors,” Electron Devices Meeting, pp. 659-663, 2009.
[9]C. H. Jan, U. Bhattacharya, R. Brain and R. Choi, “A 22 nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate Optimized for Ultra Low Power High Performance and High Density SoC Applications,” Electron Devices Meeting, pp. 1-3, 2012.
[10]S. Natarajan, M. Agostinelli, S. Akbar and A. Bowonder, “A 14nm Logic Technology Featuring 2nd-Generation FinFET Air-Gapped Interconnects Self-aligned Double Patterning and a 0.0588 µm2 SRAM Cell Size,” Electron Devices Meeting, pp. 3-7, 2014.
[11]劉傳璽，陳進來，第三版，半導體物理元件與製程-理論與實務，五南文化出版社，2006。
[12]M. Bhohr and K. Mistry, intel.com, http://goo.gl/jWz3fO, 2011.
[13]N. Patel, A. Ramesh and S. Mahapatra, “Drive Current Boosting of n-type Tunnel FET with Strained SiGe Layer at Source,” Microelectronics Journal, vol. 39, pp. 1671-1677, 2008.
[14]S. M. Sze, “Physics of Semiconductor Devices,” Wiley, 1969.
[15]Q. Huang, R. Huang and Z. Zhan, “Performance Improvement of Si Pocket-Tunnel FET with Steep Subthreshold Slope and High Ion/Ioff Ratio,” Solid-State and Integrated Circuit Technology, pp. 1-3, 2012.
[16]F. Mayer, R. Le and J. F. Damlencourt, “Impact of SOI, Si1-xGexOI and GeOI Substrates on CMOS Compatible Tunnel FET Performance,” Electron Devices Meeting, pp. 1-5, 2008.
[17]N. Dang, and C. H. Shih, “Short-Channel Effect and Device Design of Extremely Scaled Tunnel Field-effect Transistors,” Microelectronics Reliability, pp. 31-37, 2015.
[18]M. S. Kim, H. Liu and V. Narayanan, “A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter,” Electron Devices, IEEE Transactions, pp. 3661-3667, 2014.
[19]S. Datta, V. Saripalli and V. Narayanan, “Variation-Tolerant Ultra Low-Power Heterojunction Tunnel FET SRAM Design,” IEEE Computer Society, pp. 45-52, 2011.
[20]S. Migita, T. Mori, Y. Morita and W. Mizubayashi, “Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect,” Electron Device Letters, IEEE, pp. 791-794, 2014.
[21]S. Migita, T. Mori, Y. Morita and W. Mizubayashi, “Tunnel Field Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes,” Japanese Journal of Applied Physics, 04CC25, 2013.
[22]S. Migita, T. Mori, Y. Morita and W. Mizubayashi, “Synthetic Electric Field Tunnel FETs: Drain Current Multiplication Demonstrated by Wrapped Gate Electrode around Ultrathin Epitaxial Channel,” International Symposium on VLSI Technology, Systems and Applications, pp. 236-237, 2013.
[23]J. H. Seo, Y. J. Yoon, S. Lee and J. H. Lee “Design and Analysis of Si-based Arch-shaped Gate-all-around Tunneling Field Effect Transistor,” Current Applied Physics, pp. 208-212, 2015.
[24]J. D. Jackson, “Classical Electrodynamics Semiconductor,” Wiley, 1975.
[25]韓雁，第一版，半導體器件TCAD設計與應用，電子工業出版社，2013。
[26]Synopsys, TCAD Sentaurus Device Manual, H-2013.03, 2013.
[27]M. D. Martino, J. A. Martino and P. G. Agopian, “Drain Induced Barrier Thinning on TFETs with Different Source/Drain Engineering,” Microelectronics Technology and Devices, pp. 1-4, 2014.