隨著 CMOS 製程越來越先進，電晶體尺寸微縮，使可操作於更高的工作頻率，但會使電晶體對於靜電越來越敏感，靜電放電是影響積體電路可靠度的主要因素，須設計出高耐受度的靜電放電防護電路，避免積體電路遭受靜電轟擊而損壞。
靜電放電防護通常設計於輸入/出端，當應用於高頻積體電路中，須具備較低的寄生電容，否則會影響高頻電路的特性，而傳統防護元件選擇簡單的二極體，但操作頻率越來越高時，造成高頻電路特性大幅衰減，因此本論文提出藉由電阻串並聯方式使二極體產生的負載減少，並採用 CMOS 製程實踐，透過各項量測證實在單位面積下有低的高頻訊號流失和擁有足夠高的靜電放電防護能力。
因靜電也會由電源端進內部電路，所以必須有電源箝制防護電路，而電源箝制防護電路中的觸發機制被用來判斷靜電是否發生，但當內部電路上電的時間常數與靜電相近時，電阻-電容充放電機制會使排放靜電的元件意外導通，造成電源端的訊號極大流失。因此，本論文使用 CMOS 製程實踐現有電源箝制電路，分析不同的靜電放電耐受度測試、正常上電與快速上電時的可行性。

The manufacturing process becomes more advanced for high-frequency applications than before. However, the transistor is sensitive to static electricity. Therefore, it is necessary to design an electrostatic discharge (ESD) protection circuit with high ESD robustness to prevent the integrated circuit from being damaged by ESD current bombardment.
The ESD protection device is usually designed at the input/output pad. When the internal circuits are operated at high frequency, the ESD protection device should have low parasitic capacitance. Otherwise, the ESD protection device will affect the character of the high-frequency circuit. Though the simple diodes are chosen as traditional protection component, they will cause severe signal loss at higher frequency. Therefore, the thesis proposed the RC-diode ESD protection device that is adopted CMOS process to reduce signal loss through the resistor series and parallel method. As a result, the RC-diode protection device has outstanding ESD robustness and low signal loss per unit area by various testing.
Because the static electricity will also enter the internal circuit from the power supply terminal, the power-rail ESD clamp circuit is essential. The trigger mechanism in power-rail ESD clamp circuit is used to determine whether the static electricity occurs. However, the time constant of the internal circuit power-on and static electricity is close, the resistor-capacitor inverter mechanism will accidentally trigger the components of discharge current to cause significant power loss at the power supply terminal. Therefore, this thesis has adopted the CMOS process to fabricate present power-rail ESD clamp circuits for internal circuit. These power-rail ESD clamp circuits are analyzed under different testing methods of ESD robustness and discussed for internal circuit of normal and fast power-on feasibility.

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