本研究分析n型電晶體元件佈局圖對於元件之應力分佈與性能表現。該先進奈米元件之應力源主要由碳化矽材料填充於源∕汲極與具有拉伸應力之接觸蝕刻終止層組成；其中碳莫耳比例為1.65 %，接觸蝕刻終止層之拉伸應力為1.1 GPa。此研究提出一利用三維有限元素分析，模擬接觸蝕刻終止層之應力對於淺溝槽隔離上方的延伸閘極與元件通道之影響。模擬若以非製程方式考慮分析時，當延伸閘極之寬度為0.2 um時，元件載子遷移率增益之最大值約達72.5 %；分析結果指出若延伸閘極之寬度超過此尺寸，則接觸蝕刻終止層之機械應力將為元件性能表現之主要影響。若採以製程方式分析之，則當延伸閘極之寬度為0.2 um時，元件載子遷移率增益之最大值約達77.5 %，該模擬結果與相關文獻之分析趨勢符合。
另一方面，本研究亦分別以二維與三維有限元素模型採用製程順序步驟之模擬法，分析具有矽鍺通道結合接觸蝕刻終止層結構之n型電晶體元件；其中接觸蝕刻終止層分別為拉伸應力為1.1 GPa與壓縮應力－2.0 GPa。分析時固定元件通道寬度為10 um並改變元件通道長度，以觀察元件通道內之應力分佈與電性性能表現。由於二維與三維模擬趨勢相互匹配，因此可以二維模擬簡化三維模擬。與元件通道寬度與長度之比例分別為10/0.11, 10/1, 10/10 (um/um)的情形下之電性測量結果相比較，發現元件通道之應力趨勢與電性測量結果相符。此外，藉由應力模擬與電性結果可得知，在較短元件通道長度時，拉伸應力之接觸蝕刻終止層可提升元件特性；而在較長通道長度時，則為壓縮應力之接觸蝕刻終止層對於元件表現有所提升。

In this study, the effect of layout of the n-type metal-oxide field-effect transistors (nMOSFET) on the stress distribution and performance of devices was analyzed. The nMOSFET is mainly composed of silicon–carbon (SiC) stressors embedded in the source and drain (S/D) regions with the carbon mole fraction of 1.65 % and a 1.1 GPa tensile contact etch stop layer (CESL), respectively. The stress contour of device induced by CESL and the protruding gate width on shallow trench isolation was discussed by the proposed three-dimensional (3D) finite element analysis (FEA) in this research. The results revealed that as the protruding gate width is approximately 0.2 m, the maximum carrier mobility gain is about 72.5 % under the consideration of non-process flow simulation. In contrast, the maximum gain of carrier mobility achieves close to 77.5 % by using the process-flow simulation technique. The above-mentioned results match well with the simulated trends reported in the relevant literatures.
On the other hand, by means of two dimensional (2D) as well as 3D FEA process-flow simulations, the stress impacts of nMOSFETs resulted from CESL combined with the design of SiGe channel are performed. Two different stresses of CESL, 1.1 GPa and -2.0 GPa, with a fixed channel width of 10 m are used under the parametric study of channel length. The stress distribution of channel region could be completely observed during simulations. Owing to the FEA results of 2D are matched with 3D analysis, the simulated type could be simplified to 2D mode. As compared with the electrical properties measured by
the 10/0.11, 10/1, and 10/10 (m/m) of ratios for the combinations of width and length in channel region, the analytic results point out that the electrical properties are corresponded with the stress trends. Consequently, a short channel length combined with a tensile CESL could enhance it device characteristics. Moreover, a long channel length integrated with a compressive CESL could improve its electrical performance, significantly.

[1] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, New York, 2007.
[2] 劉傳璽，陳進來，半導體物理元件與製程-理論與實務，五南文化出版社，2006。
[3] 鄭晃忠，劉傳璽，新世代積體電路製程技術，東華書局，2011。
[4] C. Mahata, M. K. Bera, P. K. Bose, and C. K. Maiti, “Charge trapping characteristics in high-k gate dielectrics on germanium”, Thin Solid Films, Vol. 517, pp. 163-166, August 2008.
[5] K. Rim et al., “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs”, Electron Devices Meeting, 1995., International, pp.517-520, December 1995.
[6] Y. T. Huang, S. L. Wu, S. J. Chang, C. W. Kuo, Y. T. Chen, Y. C. Cheng, and O. Cheng, “Origin of Stress Memorization Mechanism in Strained-Si nMOSFETs Using Low Cost Stress-Memorization Technique”, IEEE Transactions on Nanotechnology, Vol. 10, No. 5, pp. 1053-1058, September 2011.
[7] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of threshold voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs”, IEEE
Electron Device Letters, Vol. 25, no. 11, pp. 731-733, November 2004.
[8] S. E. Thompson et al., “A logic nanotechnology featuring strained silicon”, IEEE Electron Device Letters, Vol. 25, pp. 191-193, March 2004.
[9] L. P. Nguyen, C. F. Beranger, G. Ghibaudo, T. Skotnicki, S. Cristoloveanu, “Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs”, Solid-State Electronics, Vol. 54, No. 2, pp. 123-130, February 2010.
[10] S. E. Thompson et al., “A 90-nm Logic Technology Featuring Strained-Silicon”, IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1790-1797, November 2004.
[11] K. Rim, R. Anderson, D. Boyd, F. Cardone, K. Chan, H. Chen, S. Christansen, J. Chu, K. Jenkins, T. Kanarsky, S. Koester, B. H. Lee, K. Lee, V. Mazzeo, A. Mocuta, D. Mocuta, P. M. Mooney, P. Oldiges, J. Ott, P. Ronsheim, R. Roy, A. Steegen, M. Yang, H. Zhu, M. Ieong, H.-S. P. Wong, “Strained Si CMOS (SS CMOS) technology: opportunities and challenges”, Solid-State Electron, Vol. 47, pp. 1133-1139, 2003.
[12] S. J. Kim, T. H. Shim, K. R. Choi, J. G. Park, “Comparative study of self-heating effect on electron mobility in nano-scale strained silicon-on-insulator and strained silicon grown on relaxed SiGe-on-insulator n-metal–oxide–semiconductor field-effect transistors”, Semiconductor Science and Technology, Vol. 24, No. 3, 2009.
[13] M. T. Currie, T. A. Langdo , G. Taraschi , E. A. Fitzgerald, D. A. Antoniadis, “Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates”, Journal of Vacuum Science & Technology B, pp. 2268-2279, November 2001.
[14] H. M. Chen, J. R. Hwang, Y. Li, F. L. Yang, “Novel Strained CMOS Devices with STI Stress Buffer Layers”, VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on, pp. 1-2, April 2007
[15] G. Eneman, M. Jurczak, P. Verheyen, T. Hoffmann, A. D. Keersgieter, K. D. Meyer, “Scalability of strained nitride capping layers for future CMOS generations”, Solid-State Device Research European Conference 2005, pp. 449-452, September 2005.
[16] S. Ito, H. Namba, T. Hirata, K. Ando, S. Koyama, N. Ikezawa, T. Suzuki, T. Saitoh, T. Horiuchi, “Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance”, Microelectronics Reliability Elsevier U.K, Vol. 42, No. 2, pp. 201-209, February 2002.
[17] M. C. Wang, H. C. Yang, W. S. Liao, H. Y. Yang, Y. Y. Hoe, K. H. Lin, S. Y. Chen, “CESL Deposition Promoting nip MOSFETs under 45-nm-node Process Fabrication”, Next-Generation Electronics,2010 International Symposium on, pp. 17-20, November 2010.
[18] W. T. Chang, J. A. Lin, C. C. Wang, W. K. Yeh, “Effect of gate capping configurations and silicon-on-insulator thickness with external stresses on partially depleted metal-oxide-semiconductor field-effect transistors”, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 29, pp. 01A904-01A904-4, January 2011.
[19] G. Eneman, P. Verheyen, A. D. Keersgieter, M. Jurczak, and K. D. Meyer, “Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study”, IEEE Transactions on Electron Devices, Vol. 54, No. 6, June 2007.
[20] P. Verheyen, V. Machkaoutsan, M. Bauer, D. Weeks, C. Kerner, F. Clemente, H. Bender, D. Shamiryan, R. Loo, T. Hoffmann, P. Absil, S. Biesemans, and S. G. Thomas, “Strain Enhanced nMOS Using In Situ Doped Embedded Si1−xCx S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process”, IEEE Electron Device Letters, Vol. 29, No. 11, pp. 1206-1208, November 2008.
[21] K. J. Chui, K. W. Ang, N. Balasubramanian, M. F. Li, G. S. Samudra, Y. C. Yeo, “n-MOSFET With Silicon–Carbon Source/Drain for Enhancement of Carrier Transport”, IEEE Transactions on Electron Devices, Vol. 54, No. 2, February 2007.
[22] V. Chan, K. Rim, M. Ieong, S. Yang, R. Malik, Y. W. Teh, M. Yang, Q. Ouyang, “Strain for CMOS performance Improvement”, IEEE 2005 Custom Integrated Circuits Conference, pp. 667-674, September 2005.
[23] C. C. Lu, J. J. Huang, W. C. Luo, T. H. Hou, and T. F. Lei, “Strained Silicon Technology: Mobility Enhancement and Improved Short Channel Effect Performance by Stress Memorization Technique on nFET Devices”, Journal of The Electrochemical Society, Vol. 157, No. 5, pp. 497-500, 2010.
[24] C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd, P. Stolk, F. Boeuf, F. Arnaud, “Stress Memorization Technique (SMT) Optimization for 45nm CMOS”, VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on, pp. 78-79, 2006.
[25] C. C. Liao, T. Y. Chiang, M. C. Lin, T. S. Chao, “Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism”, IEEE Electron Device Letters, Vol.31, pp. 281-283, April 2010.
[26] C. S. Smith, “Piezoresistance Effect in Geruianium and Silicon”, Physics Review, Vol. 94, pp. 42-49, 1954.
[27] Y. C. Yeo, Q. Lu, T. J. King, C. M. Hu, T. Kawashima, M. Oishi, S. Mashiro, J. Sakai, “Enhanced Performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Germanium”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, pp. 753-756, 2000.
[28] W. S. Liao, Y. G. Liaw, M. C. Tang, K. M. Chen, S. Y. Huang, C. Y. Peng, C. W. Liu, “PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD-SiNx Stressing Layer”, IEEE Electron Device Letters, Vol.29, No. 1, pp. 86-88, January 2008.
[29] L. Washington, F. Nouri, S. Thirupapuliyur, G. Eneman, P. Verheyen, V. Moroz, L. Smith, X. Xu, M. Kawaguchi, T. Huang, K. Ahmed, M. Balseanu, L. Q. Xia, M. Shen, Y. Kim, R. Rooyackers, K. D. Meyer, R. Schreutelkamp, “pMOSFET With 200% Mobility Enhancement Induced by Multiple Stressors”, IEEE Electron Device Letters, Vol. 27, No. 6, June 2006.
[30] Howard C. H. Wang, S. H. Huang, C. W. Tsai, H. H. Lin, T. L. Lee, S. C. Chen, C. H. Diaz, M. S. Liang and J. Y. C. Sun, “High-Performance PMOS Devices on (110)/<111’> Substrate/Channel with Multiple Stressors”, Electron Devices Meeting, 2006. IEDM '06. International, pp. 1-4, December 2006.
[31] W. C. Wang, S. T. Chang, J. Huang, S. H. Liao, C. Y. Lin, “3D Simulations of Width Effect on Performance in NMOSFETs with SiC S/D Stressors and CSEL Linear”, Electron Devices and Solid-State Circuits, 2007. IEEE Conference on, pp. 1071-1074, December 2007.
[32] Saeed Moaveni, “Finite Element Analysis: Theory and Application with Ansys”, Pearson Education/Prentice Hall, 2005.
[33] 劉晉奇，褚晴暉，有限元素分析與ANSYS的工程應用，滄海書局，2006。
[34] K. N. Chiang, C. H. Chang, C. T. Peng, “Local-strain effects in Si/SiGe/Si islands on oxide”, Applied Physics Letters, Vol. 87, Issue 19, 2005.
[35] Ansys Mechanical APDL Programmer’s Manual.
[36] 林坤楠，材料力學，滄海書局，2009。
[37] Jeff Wu, Xin Wang, “Stress Engineering for 32 nm CMOS Technology Node”, Solid-State and Integrated-Circuit Technology, 2008. 9th International Conference on, pp.113-116, October 2008.
[38] Ferdinand P.Beer, E. Russell Johnson Jr., John T. DeWolf, “Mechanics of material 3rd edition”, Mc-Graw Hill.
[39] K.V. Loiko, V. Adams, D. Tekleab, B. Winstead, X. Z. Bo, P. Grudowski, S. Goktepeli, S. Filipiak, B. Goolsby, V. Kolagunta, and M.C. Foisy “Multi-Layer Model for Stressor Film Deposition”, Simulation of Semiconductor Processes and Devices, 2006 International Conference on, pp. 123-126, September 2006.