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研究生: 洪若純
Hong, Ruo-Chun
論文名稱: 鐵電氧化鉿鋯記憶體特性及其應用
Ferroelectric HfZrOx Characteristics and Memory Applications
指導教授: 李敏鴻
Lee, Min-Hung
學位類別: 碩士
Master
系所名稱: 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2018
畢業學年度: 106
語文別: 中文
論文頁數: 81
中文關鍵詞: 鉿基氧化物鐵電電晶體深度學習訓練
英文關鍵詞: Hafnium-based Oxides, FeFET, deep learning training
DOI URL: http://doi.org/10.6345/THE.NTNU.EPST.004.2018.E08
論文種類: 學術論文
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  • 近幾年來,鐵電材料已經被廣泛的使用,其應用在鐵電材料記憶體(Ferroelectric Random-Access Memory, FeRAM)上最多,因此被當成新興技術之非揮發性記憶體之一。鐵電閘極場效式電晶體(Ferroelectric Field Effect Transistor, FeFET)具有許多優點,如讀寫速度快、操作電壓低…等特性。雖然有著眾多優點但在過去,傳統鈣鈦礦鐵電材料,如Pb (ZrxTi1-x) O3 (PZT)和BaTiO3 (BTO)等有機材料一直無法直接整合於現今CMOS(Complementary Metal-Oxide-Semiconductor)技術上。經過多年研究發現若是使用二氧化鉿為基底,既能展現出鐵電材料之特性,又是能使用在CMOS技術上的高介電係數材料。
    本研究將主題分為三個部分,第一部分為探討鐵電Hf1-xZrxO2場效應電晶體與鰭式電晶體,兩者在高數據保持率(Retention)和讀取耐久性(Endurance)的結果與差異;第二部分為在具有鐵電層的元件上,使用各種方式施加偏壓使鐵電極化翻轉,量測出穿隧現象;第三部分為利用具有鐵電特性元件,透過不同波型模組設定做深度學習觀察其差異及變化。

    In recent years, ferroelectric material has been extensively investigated. Hf-based oxide materials with ferroelectricity have the potential for application on FeRAM. Therefore, it is considered as one of the non-volatile memory candidates of emerging technologies. The FeFET (Ferroelectric Field Effect Transistor) has many advantages, such as fast read and write speeds, low operation voltage, and high endurance operation. Conventional Perovskite-type ferroelectric material, such as BaTiO3 (BTO) and Pb (ZrxTi1-x) O3 (PZT), has the issues of the process compatibility and scaling down for FeRAM applications. The HfO2-based with ferroelectricity may for CMOS applications due to process compability.
    The subject of this study will be divided into three parts. The first part is the results of ferroelectric Hf1-xZrxO2 planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and FinFET (Fin Field-Effect Transistor) for data retention and endurance. The second part is FTJ (Ferroelectric Tunneling Junction) including the dependence on voltages, HZO thickness, and interface treatment in chapter 3. The third part is deep learning (training) of FeFET and MFM in chapter 4.

    Publication I 中文摘要 II Abstract III 致謝 IV 目錄 V 圖目錄 VII 表目錄 XII 第一章 緒論 1 第二章 鐵電HZO FeFET特性 4 2-1 簡介 4 2-2 鐵電HZO FeFET特性的結果與討論 6 2-2-1 Retention波型設定 6 2-2-2 HZO FeFET 5 nm及7 nm Retention結果 7 2-2-3 Endurance波型設定 13 2-2-4 HZO FeFET 5 nm及7 nm Endurance結果 15 2-2-5 室溫下Endurance 和 Retention總結 19 2-2-6 HZO 7 nm FeFET 85℃ Retention和Endurance結果 21 2-2-7 Planar FeFET結論 25 2-2-8 FinFET Retention與Endurance波型設定 26 2-2-9 FinFET 5 nm Retention與Endurance結果 27 2-3 結論 36 第三章 鐵電穿隧接面元件(FTJ) 39 3-1 介電層導電機制 39 3-2 穿隧機制 39 3-3 FTJ原理 40 3-4 文獻探討 41 3-5 量測方法 43 3-6 量測材料及元件製作 50 3-7 結論 59 第四章 類比記憶體之深度學習 61 4-1 何謂深度學習 61 4-2 文獻探討 63 4-3 深度學習的波型設定及結果 65 4-4 結論 76 第五章 總結論與未來工作 78 5-1 總結論 78 5-2 未來工作 79 參考文獻 80

    [1]《科學發展》2018年1月,541期,30 ~ 36頁(2018/06/25)
    [2] 各式記憶體簡介,李明道,奈米通訊22卷No.4 (2018/06/25)
    [3] K. Ni, M. Jerry, J. A. Smith, and S. Datta, “A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs, ” VLSI Technology Symp., Jun. 2018, pp. 131-132.
    [4] J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectric Zr0.5Hf0.5O2 Thin Films for Nonvolatile Memory Applications, ” Appl. Phys. Lett., vol. 99, pp. 112901, Sep. 2011.
    [5] S. Salahuddin and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices, ” NanoLetters, vol. 8, no. 2, pp. 405-410, Dec. 2008.
    [6] S. Salahuddin and S. Datta, “Can the Subthreshold Swing in a Classical FET be Lowered Below 60 mV/decade? ” IEDM Tech. Dig., Dec. 2008, pp. 693-696.
    [7] T. P.-C. Juan, C.-Y. Chang, and J. Y.-M. Lee, “A New Metal–Ferroelectric (PbZr0.53Ti0.47O3)–Insulator (Dy2O3)–Semiconductor (MFIS) FET for Nonvolatile Memory Applications, ” IEEE Electron Device Lett., vol. 27, no. 4, pp.217-220, Apr. 2006.
    [8] T. S. Bösckea, J. Müllerb, D. Bräuhausc, U. Schröderd, U. Böttgerc, “Ferroelectricity in Hafnium Oxide: CMOS Compatible Ferroelectric Field Effect Transistors, ” IEDM Tech. Dig., Dec. 2011, pp. 547-550.
    [9] Qimonda AG, Integrated Circuit with Dielectric Layer, U.S. Patent No. 14, 7709359B2 (4 May, 2010)
    [10] J. Müller, E. Yurchuk, T. Schlösser, J. Paul, R. Hoffmann, S. Müller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kücher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schröder and T. Mikolajick, “Ferroelectricity in HfO2 Enables Nonvolatile Data Storage in 28 nm HKMG,” VLSI Technology Symp., Jun. 2012, pp. 25-26.
    [11] C. H. Cheng, and A. Chin, “Low-Voltage Steep Turn-On PMOSFET Using Ferroelectric High-K Gate Dielectric, ” IEEE Electron Device Lett., vol. 35, no. 2, pp.274-276, Jan. 2014.
    [12] M. H. Park, H. J. Kim, Y. J. Kim, T. Moon, K. D. Kim, and C. S. Hwang, “Toward a Multifunctional Monolithic Device Based on Pyroelectricity and The Electrocaloric Effect of Thin Antiferroelectric HfxZr1−xO2 films, ” Nano Energy, vol. 12, pp.131-140, Dec. 2015.
    [13] R. Eskandari, X. Zhang, and L. M. Malkinski, “Polarization-Dependent Photovoltaic Effect in Ferroelectric-Semiconductor System, ” Appl. Phys. Lett., vol. 110, pp. 121105, Mar. 2017.
    [14] M. H. Lee, Y.-T. Wei, C. Liu, J.-J. Huang, M. Tang, Y.-L. Chueh, K.-Y. Chu, M.-J. Chen, H.-Y. Lee, Y.-S. Chen, L.-H. Lee, and M.-J. Tsai, “Ferroelectricity of HfZrO2 in Energy Landscape with Surface Potential Gain for Low-Power Steep-Slope Transistors, ” IEEE Trans. Electron Devices, Vol. 3, No. 4, pp. 377-381, Jul. 2015.
    [15] M. H. Lee, Y.-T. Wei, K. Y. Chu, J. J. Huang, C. W. Chen, C. C. Cheng, M. J. Chen, H. Y. Lee, Y. S. Chen, L. H. Lee, and M. J. Tsai, “Steep Slope and Near Non-Hysteresis of FETs with Antiferroelectric-Like HfZrO for Low-Power Electronics, ” IEEE Trans. Electron Devices, Vol. 36, No. 4, pp. 294-296, Apr. 2015.
    [16] L.V. Hai, M. Takahashi and S. Sakai, “Downsizing of Ferroelectric-Gate Field-Effect-Transistors for Ferroelectric-NAND Flash Memory Cells, ” IEEE Non-Volatile Semiconductor Memory Workshop, May. 2011.
    [17] Y.-C. Chiu, C.-H. Cheng, C.-Y. Chang, M.-H. Lee, H.-H. Hsu, and S.-S. Yen, “Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/Decade Operation, Fast 20ns Speed, and Robust 85°C Extrapolated 1016 Endurance, ” VLSI Technology Symp., Jun. 2015, pp. 184-185.
    [18] www2.nsysu.edu.tw/IEE/lou/elec/web/process/semi.htm (2018/05/20)
    [19] www.ndl.org.tw/docs/publication/23_1/D4 (2018/05/20)
    [20] X. Tian, S. Shibayama, T. Nishimura, T. Yajima, S. Migita and A. Toriumi, “Tunneling Electro-Resistance Effect in Ultra-Thin Ferroelectric HfO2 Junctions, ” Solid State Devices and Materials, Sep. 2016, pp. 625-626.
    [21] 深度學習https://zh.wikipedia.org/wiki(2018/06/22)
    [22] http://research.sinica.edu.tw/deep-learning-2017-ai-month/ (2018/06/22)
    [23] M. Jerry, P.-Y. Chen, J. Zhang, P. Sharma, K. Ni, S. Yu, and S. Datta, “Ferroelectric FET Analog Synapse for Acceleration of Deep Neural Network Training, ” IEDM Tech. Dig., Dec. 2017, pp. 140-142.

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