本研究是將鋯加入氧化釔 (Y2O3+Zr)作為氧化層的高介電係數薄膜材料，並成功的製作出MOS電容器。由於氧化釔和其它高介電係數薄膜材料相比，釔很容易跟矽基板產生相互擴散的現象，而鋯本身不僅是高介電係數薄膜材料且鋯和矽之間，有良好的介面品質。並針對本實驗製作出來的MOS電容器的電性和物性做分析與探討。
本研究沉積薄膜的方式是使用射頻共濺鍍技術，在常溫且充滿氬氣的真空腔體，將高純度的氧化釔和鋯之靶材，依照不同的條件濺射沉積在矽基板上，形成一層厚度7奈米的氧化釔/鋯薄膜，之後在充滿氮氣的真空腔體中，分別執行550 ℃、700 ℃和850 ℃的快速熱退火 (RTA)，接著鍍上氮化鋯/鈦/鋁，製成閘極電極。最後再利用電流-電壓 (I-V)、電容-電壓 (C-V)、原子力顯微鏡 (AFM)和X光繞射儀 (XRD)等，分析探討氧化釔/鋯薄膜的電性和物性。
研究結果顯示，氧化釔/鋯薄膜擁有良好的結晶溫度 (約850 ℃)、介電係數和低的閘極漏電流，在經過700 ℃的快速熱退火後，得到的相對介電係數為14.7，閘極漏電流方面，閘極注入電壓為-1 V時，漏電流大小約為10-5 ~ 10-6 A/cm2，基板注入電壓為1 V時，漏電流大小約在10-5 ~ 10-6 A/cm2，漏電流機制符合蕭基發射，其閘極和介電層間、介電層和矽基板之間的蕭基能障分別為1.15 eV及1.01 eV。

In this study the Y2O3 integrated with Zr was regarded as high-k dielectric material for oxide layer and the MOS capacitance was successfully fabricated. Compared with others high-k dielectric material, the Y2O3 has inter-diffusion phenomenon with silicon. However the Zr is not only a high-k dielectric material but also a good quality of interface with silicon. The electrical and physical characteristics of the MOS capacitances were analyzed and discussed in this study.
The high-k Y2O3 and Zr thin films (7 nm) were deposited by RF co-sputtering technique using highly pure Y2O3 and Zr as the sputtering targets in Ar ambient at room temperature, followed by RTA at 550, 700 or 850 ℃ in N2 ambient. ZrN/Ti/Al was then formed as the gate electrode. The electrical and physical properties of the capacitors were evaluated through I-V (current-voltage), C-V (capacitance-voltage), AFM, XRD.
The results revealed that the Y2O3 and Zr thin films have satisfactory crystallization temperature (about 850 ℃), dielectric constant (EOT=1.86), and gate leakage current. The relative dielectric constant of the Y2O3/ Zr film is 14.7 after 700 ℃ rapid thermal annealing. The gate leakage current is 10-5-10-6 or 10-5-10-6 A/cm2 at a gate bias of 1 or -1 V, respectively. Moreover, the Schottky barrier height at the gate/oxide interface or oxide/p-Si interface is about 1.15 or 1.01 eV, respectively.

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