研究生: |
紀凱文 Ji, Kai-Wun |
---|---|
論文名稱: |
摺積神經網路全連結層FPGA實現之研究 The FPGA Implementation of Fully-connected Layers of Convolutional Neural Networks |
指導教授: |
吳榮根
Wu, Jung-Gen 黃文吉 Hwang, Wen-Jyi |
學位類別: |
碩士 Master |
系所名稱: |
資訊工程學系 Department of Computer Science and Information Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 62 |
中文關鍵詞: | 類神經網路 、全連結 、摺積神經網路 |
DOI URL: | https://doi.org/10.6345/NTNU202204029 |
論文種類: | 學術論文 |
相關次數: | 點閱:145 下載:27 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文旨在於FPGA ( Field Programmable Gate Array ) [1] [2]平台設計實現全連結架構,並與摺積神經網路結合,成為高速的人工視覺辨識系統。
本論文之基礎建立於類神經網路之全連結的使用,除了將全連結硬體化之外,並與具有即時運算的能力摺積神經網路(Convolutional Neural Network)整合。現存的摺積神經網路系統大多以GPU實現,雖具有高速的運算,但同時也擁有高功率消耗等缺點。雖然以FPGA為主之設計可有效降低功率消耗,但也有許多可改善之處。首先是在運算過程中會產生許多的中繼結果,這會使記憶體增加儲存資料之負擔;其次是現有硬體實現之架構僅具焦於摺積神經網路內的摺積層架構,往往忽略了其他重要架構像是全連接層(Fully-Connected Layer)之設計,根據上述原因導致無法實現高速及高準確度之人工視覺系統。
本系統採用全連結架構做為硬體實現,此架構大致上可分為2個全連結層,利用將這2個層級硬體化,進而實現高速的全連結運算。除了實現高速運算之外,為了提高此系統的辨識率,將以此架構與摺積神經網路整合,使辨識率大幅增加。此系統通常應用於字元及人臉辨識,透過我們的實驗結果顯示此架構適合使用於需要高速運算、高準確度、高可攜度、低功率消耗等的人工視覺辨識系統之應用程式。
[1] S. Hauck and A. Dehon, Reconfigurable Computing: The Theory and Practice of FPGABased, 2008.
[2] U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 4th Ed.,, 2014.
[3] Y. LeCun, L. Bottou, Y. Bengio, and P. Haffner, Gradient-Based Learning Applied to Document Recognition. Proceedings of the IEEE, 86, pp. 2278-2324, 1998.
[4] Y. LeCun, Y. Bengio and G. Hinton, Deep Learning, Nature, 521, pp. 436-444, 2015.
[5] C. Farabet, B. Martini, B. Corda, P. Akselrod, E. Culurciello, and Y. LeCun, Neuflow: A Runtime Reconfigurable Dataflow Processor for Vision. In Proc. IEEE Workshop Embedded Comput. Vision., 2011.
[6] J. Jin, V. Gokhale, A. Dundart, B. Krishnamurthy, B. Martinit and E. Culurciello, An Efficient Implementation of Deep Convolutional Neural Networks on a Mobile Coprocessor. In Proc. IEEE Int. Midwest Symp. on Circuits and Systems, pp.133-136., 2014.
[7] S. Chakradhar, M. Sankaradas, V. Jakkula, and S. Cadambi, A Dynamically Configurable Coprocessor for Convolutional Neural Networks. In Proc. ACM Int. Symp. on Comput Architecture, pp. 247-257., 2010.
[8] C. Farabet, C. Poulet, J. Y. Han, and Y. LeCun, CNP: An FPGA-Based Processor for Convolutional Networks. In Proc. IEEE Int. Conf. Field Programmable Logic and App., pp. 32-37., 2009.
[9] M. Sankaradas, V. Jakkula, S. Cadambi, S. Chakradhar, I. Durdanovic, E. Cosatto, and H. P.Graf, A Massively Parallel Coprocessor for Convolutional Neural Networks. In Proc. IEEE Int. Conf.on Application-Specific Syst., Arch. and Proc., pp. 53-60., 2009.
[10] C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong, Optimizing FPGA-Based Accelerator Design for Deep Convolutional Neural Networks. In Proc. ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, pp.161-170., 2015.
[11] Y. Cheng, F. X. Yu, R. Feris, S. Kumar, A. Choudhary, and S.-F. Chang, An Exploration of Parameter Redundancy in Deep Networks with Circulant Projections. In Proc. IEEE Int. Conf. Comput. Vision., 2015.
[12] 王雅慶, 以FPGA實現摺積神經網路及應用於人臉特徵辨識之研究,國立台灣師範大學碩士論文, 2016.
[13] Carl Latino, Marco A. Moreno-Armendariz, and Martin Hagan, Realizing General MLP Networks with Minimal FPGA Resources. In Proc. IEEE Int. Joint Conf. on Neural Net., pp. 1722-1729., 2009.
[14] Y. Jia, E. Shelhamer, J. Donahue, S. Karayev, J. Long, R. Girshick, S. Guadarrama, and T. Darrell, Caffe: Convolutional Architecture for Fast Feature Embedding. In Proc. ACM Int. Conf. on Multimedia, pp. 675-678., 2014.