這是實驗並且整合在epi Ge/Si FET加上鐵電閘極介電層HfZrOx的堆疊後，藉由負電容的影響讓電晶體無磁滯效應且次臨界擺幅（SS）< 60mV/dec。半導體和鐵電的電容相匹配，獲得Vt 在正掃及反掃無遲滯效應的結果。分別藉由body factor和模擬的執行，來驗證負電容的效應和透過數值計算的方式來進行Ge厚度的最佳化。
於本論文認定文獻中之鰭式電晶體(FinFET)為鰭寬小於50奈米，本團隊所製程之鰭寬~60-80nm，故稱鰭型電晶體(Fin-Shaped FET)，鰭型的結構有利於閘極的控制能力獲得陡峭的次臨界斜率，第三章研究了兩種鰭線寬的微縮方式，此實驗的目標在於能在六吋的製程中達到理想之耐米鰭線寬度。
一般鰭型穿隧型電晶體的製程中，會使用兩個獨立的光罩來的定義源極和汲極，再分別離子佈植不同的區域，但這樣會讓源極和汲極間留有一段本質區域，造成能帶到能帶間的穿隧(band-to-band tunneling, BTBT)機率下降，在本研究中製作出奈米鰭線寬使用I-line 黃光製程而非E-beam直寫，利用自對準製程技術(self-alignment process)使得源極和汲極和閘極間無本質區域的方法成功的被驗證。

關鍵字: 陡峭次臨界擺幅、鰭型電晶體、鰭型穿隧型電晶體

This is experimental demonstration integrating Ge FETs with ferroelectric HfZrOx gate stack for subthreshold swing (SS) < 60mV/dec and hysteresis-free by negative capacitance (NC) effect. The capacitance of semiconductor and ferroelectricity is matched to obtain the no VT shift for forward and reverse sweeps with hysteresis-free. The body factor and modeling are performed to validate the NC effect and optimize the Ge thickness by numerical calculation, respectively.
The FinFET with the fin width less than 50nm is as well know. The fin width of this work is ~60-80nm, therefore, we denoted our FET as fin-shaped FET. The small body volume of Fin-shaped is beneficial for well-control by gate to obtain steep threshold slope.The third chapter of this thesis introduces two types of fin width formation by conventional I-line stepper. The goal of this work is the narrow fin width to be achieved by NDL standard 6” process line.
The conventional process of TFET have to individual mask for source and/or drain with different ion implant (I/I) species, this may lead the space between gate to source/drain, which may lead lower BTBT. In this work, the narrow fin process using all I-line photolithograph stepper without e-beam writer is proposed. The self-aligned I/I process for source/drain and no space between gate to source/drain will be demonstrated.

Keyword: steep subthreshold swing, fin-shaped FET, fin-shaped TFET.

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