研究生: |
吳建平 Wu, Jian-Ping |
---|---|
論文名稱: |
採用四位元電阻式閘極鰭式電晶體的仿生計算平台 A Neuromorphic-Computing Platform with Four-Bit-Per-Cell Resistive-Gate FinFET |
指導教授: |
劉傳璽
Liu, Chuan-Hsi 莊紹勳 Chung, Shao-Shiun |
口試委員: |
張廖貴術
Chang-Liao, Kuei-Shu 郭治群 Guo, Jyh-Chyurn 莊紹勳 Chung, Shao-Shiun 劉傳璽 Liu, Chuan-Hsi |
口試日期: | 2022/05/06 |
學位類別: |
碩士 Master |
系所名稱: |
機電工程學系 Department of Mechatronic Engineering |
論文出版年: | 2022 |
畢業學年度: | 110 |
語文別: | 中文 |
論文頁數: | 85 |
中文關鍵詞: | 電阻式閘極鰭式電晶體 |
英文關鍵詞: | RG-FinFET |
研究方法: | 實驗設計法 |
DOI URL: | http://doi.org/10.6345/NTNU202200473 |
論文種類: | 學術論文 |
相關次數: | 點閱:82 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本研究首先利用電阻式記憶體 (RRAM) 和鰭式電晶體 (FinFET),建構出電阻式閘極鰭式電晶體 (RG-FinFET) 的架構。RG-FinFET 的記憶體結構是將一個電阻式記憶體串接在高介電係數鰭式電晶體的閘極,藉由調變 RRAM 的阻態以切換 FinFET,從而通過 RG-FinFET的汲極電流來區分內部儲存的狀態。
在 RRAM 元件特性上,因有 HfON 作為介電層,具有無須Forming的特性,不需要太大的電流即可操作,能大幅降低功耗,且有良好的穩定性。與FinFET整合成電阻式記憶體之後的 RG-FinFET 可以在超低電流下操作。操作速度方面,最快能在 10 奈秒內完成 SET,在 4 奈秒內完成 RESET。除此之外,此元件能利用較小的脈衝電壓來達成對稱的漸變式操作,此記憶體最大與最小的讀出電流比有 106 倍,可明確區分成16個狀態 (4-bit-per-cell)。在可靠度的測試中,16個狀態都可以操作超過 105 次,且預估在 138°C 的高溫烘烤下可以維持十年。RG FinFET 在記憶體陣列中的特性也加以評估,內部閘極電介質可以有效防止潛行路徑 (sneak path),避免資訊從鄰近單元流失。在電性干擾的分析中,不論是編程或讀取的干擾,都具有很好的抗干擾能力。
其次,本研究將 RG-FinFET 作為基本元件,建構出全由電阻所組成的神經仿生計算平台,此平台包含權重儲存、激發函數電路以及類比數位轉換器,皆是以 RG-FinFET 為核心完成。本研究提出的阻式整流線性單位函式 (rReLU) 的功能相當理想,電阻式類比數位轉換器 (rADC) 也有很好的轉換結果,向全電阻式仿生計算平台 (FRNC) 的發展更近了一步。
We complete the architecture of the resistive-gate FinFET (RG-FinFET) with an integration of Resistance Random Access Memory (RRAM) and a FinFET. The RG-FinFET is a structure which connects an RRAM and the gate of high-k FinFET in series. By modulating the resistance of the RRAM, we can change the states of the FinFET. In other words, we can distinguish the 0 and 1 states and store the states from the varying drain currents of the RG-FinFET.
In terms of the RRAM characteristics, because HfON is used as a dielectric layer, it has a characteristic of forming-free. It requires less current to operate, which can greatly reduce power consumption and has good stability. As a unit cell of RG-FinFET, it can operate at ultra-low current. In terms of operation speed, the SET operation can be completed in 10 nanoseconds, and the RESET can be completed in 4 nanoseconds. In addition, this device can achieve symmetrical gradual operation with a small pulse voltage. The maximum and minimum read current ratio of the memory is 10^6 times, which can be clearly distinguished into 16 states (4-bit-per-cell). For the reliability test, 16 states can be operated more than 10^5 times, and it is estimated that it can last for ten years under the high temperature baking of 138°C. The characteristics of RG FinFETs in memory arrays are also evaluated, and the internal gate dielectrics can effectively prevent sneak path, preventing information loss from adjacent cells. For the analysis of disturb, whether it is programming or reading, it has good disturb immune ability.
Furthermore, in this work, we used RG-FinFET as the basic component to construct a neuromorphic computing platform composed of resistors. This platform includes weight storage, activation function circuit, and analog-to-digital converter, all of which are constructed by the using of RG-FinFET. The resistive rectification linear unit function (rReLU) proposed in this study works quite well. The resistive analog-to-digital converter (rADC) also has good conversion results. As a result, we are one step closer to a fully resistive neuromorphic computing platform (FRNC).
[1.1] M. H. White, D. A. Adams, and J. Bu, “On the Go with SONOS,” IEEE Circuits and Devices Magazine, Vol. 16, pp. 22-31, 2000.
[1.2] R. Guo, Y. Liu, S. Zheng, S. Y. Wu, P. Ouyang, W. S. Khwa, X. Chen, J. J. Chen, X. Li, and L. Liu, "A 5.1 pJ/neuron 127.3 us/inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS," 2019 Symposium on VLSI Circuits, pp. 120-121, 2019.
[1.3] V. P. H. Hu, H. H. Lin, Z. A. Zheng, Z. T. Lin, Y. C. Lu, L. Y. Ho, Y. W. Lee, C. W. Su, and C. J. Su, "Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications," 2019 Symposium on VLSI Technology, pp. 134-135, 2019.
[1.4] N. Xu, Y. Lu, W. Qi, Z. Jiang, X. Peng, F. Chen, J. Wang, W. Choi, S. Yu, and D. S. Kim, "STT-MRAM Design Technology Co-optimization for Hardware Neural Networks," 2018 IEEE International Electron Devices Meeting (IEDM), pp. 348-351, 2018.
[1.5] I. Giannopoulos, A. Sebastian, M. Le Gallo, V. Jonnalagadda, M. Sousa, M. Boon, and E. Eleftheriou, "8-bit Precision in-Memory Multiplication with Projected Phase-Change Memory," 2018 IEEE International Electron Devices Meeting (IEDM), pp. 628-631, 2018.
[1.6] H. Wu, X. H. Wang, B. Gao, N. Deng, Z. Lu, B. Haukness, G. Bronner, and H. Qian, “Resistive Random Access Memory for Future Information Processing System,” Proceedings of the IEEE, Vol. 105, pp.1770-1789, 2017.
[1.7] S. Yu, Resistive Random Access Memory (RRAM), Morgan & Claypool, 2016.
[1.8] H. D. Crane, “The Neuristor,” IRE Transactions on Electronic Computers (TEC), Vol. EC-9, pp. 370-371, 1960.
[1.9] C. Mead, “Neuromorphic Electronic Systems,” Proceedings of the IEEE, Vol. 78, pp. 1629-1636, 1990.
[1.10] S. S. Sheu, M. F. Chang, K. F. Lin, C. W. Wu, Y. S. Chen, P. F. Chiu, C. C. Kuo, Y. S. Yang, P. C. Chiang, W. P. Lin, C. H. Lin, H. Y. Lee, P. Y. Gu, S. M. Wang, F. T. Chen, K. L. Su, C. H. Lien, K. H. Cheng, H. T. Wu, T. K. Ku, M. J. Kao, and M. J. Tsai, “A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 200-201, 2011.
[1.11] S. S. Chung, E R. Hsieh, S P. Yang, and C. H. Chuang, “A Novel One Transistor Non volatile Memory Feasible for NOR and NAND Applications in IoT Era,” IEEE Silicon Nanoelectronics Workshop (SNW), pp. 44-45, 2016.
[1.12] A. K alantarian , G. Bersuker , D. C. Gilmer, D. Veksler, B. Butcher, A. Padovani, O. Pirrotta, L. Larcher, R. Geer, Y. Nishi, and P. Kirsch, “Controlling Uniformity of RRAM Characteristics Through the Forming Process,” IEEE International Reliability Physics Symposium (IRPS), pp. 6C.4.1-6C.4.5, 2012
[1.13] S. Yu, Zhiwei Li, P. Y. Chen1, H. Wu, B. Gao, D. Wang, W. Wu, and H. Qian, “Binary Neural Network with 16 Mb RRAM Macro Chip for Classification and Online Training,” 2016 IEEE International Electron Devices Meeting (IEDM), pp. 416-419, 2016.
[2.1] H-S. P. Wong, H. Y. Lee, S. Yu, Y. S. Chen, Y. Wu, Chen, P. S. Chen, B. Lee, and M. J. Tsai, “Metal–Oxide RRAM,” Proceedings of the IEEE, Vol. 100, No. 6, pp.1951-1970, 2012.
[2.2] J. Woo, K. M oon, J. Song, M. Kwak, J. Park, and H. Hwang, “Optimized Programming Scheme Enabling Linear Potentiation in Filamentary HfO2 RRAM Synapse for Neuromorphic Systems,” IEEE Transactions on Electron Devices, vol. 63, No. 2016, pp. 5064-5067, 2016.
[3.1] B. Gao, H. Wu, W. Wu, X. Wang, P. Yao, Y. Xi, W. Zhang, N. Deng, P. Huang, and X. Liu, “Modeling Disorder Effect of the Oxygen Vacancy Distribution in Filamentary Analog RRAM for Neuromorphic Computing,” 2017 IEEE Transactions on Electron Devices, pp. 91-94, 2017.
[3.2] D. Ielmini, “Modeling the Universal Set/Reset Characteristics of Bipolar RRAM by Field-and Temperature-Driven Filament Growth,” IEEE Transactions on Electron Devices, vol. 58, pp. 4306-4317, 2011.
[3.3] W. Kim, S. Il Park, Z. Zhang, Y. Y. Liauw, D. Sekar, H. S. Philip Wong, and S. S. Wong, “Forming-Free Nitrogen-Doped AlOX RRAM with Sub-μA Programming Current,” 2011 Symposium on VLSI Technology, pp. 22-23, 2011.
[3.4] W. Wu, H. Wu, B. Gao, N. Deng, S. Yu, and H. Qian, “Improving Analog Switching in HfOx Based Resistive Memory with a Thermal Enhanced Layer,” IEEE Electron Device Letters, vol. 38, No 8, pp. 1019-1022, 2017.
[4.1] X. Zhong, K. Cai, G. Song, and N. Raghavan, “Deep Learning Based Detection for Mitigating Sneak Path Interference in Resistive Memory Arrays,” 2020 IEEE International Conference on Consumer Electronics - Asia (ICCE-Asia), 2020.
[5.1] S. Song and A. Das, “A Case for Lifetime Reliability-Aware Neuromorphic Computing,” 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 596-598, 2020.
[6.1] E. R. Hsieh, X. Zheng, B. Q. Le, Y. C. Shih, R. M. Radway, M. Nelson, S. Mitra, and S. Wong, “Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array,” IEEE Electron Device Letters, vol. 42, pp. 335-338, 2021.
[6.2] W. Y. Yang, E. R. Hsieh, C. H. Cheng, B. Y. Chen, K. S. Li, and S. S. Chung, “A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path,” IEEE International Reliability Physics Symposium (IRPS), p. 5D.5, 2021.
[6.3] E. R. Hsieh, K. T. Chen, P. Y. Chen, S. S. Wong, and S. S. Chung, “A FORMing-Free HfO2/HfON-Based Resistive-Gate Metal–Oxide–Semiconductor Field-Effect-Transistor (RG-MOSFET) Nonvolatile Memory with 3-Bit-Per-Cell Storage Capability,” IEEE Transactions on Electron Devices (TED), vol. 68, pp. 2699-2704, 2021.
[6.4] B. Q. Le, A. Levy, T. F. Wu, R.t M. Radway, E. R Hsieh, X. Zheng, M. Nelson, P. Raina, H. S. Philip Wong, S. Wong, and S. Mitra, “RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays,” IEEE Transactions on Electron Devices (TED), vol. 68, pp. 4397-4403, 2021.
[6.5] Y. Feng, P. Huang, Y. Zhao, Y. Shan, Y. Zhang, Z. Zhou, L. Liu, X. Liu, and J. Kang, “Improvement of State Stability in Multi-Level Resistive Random-Access Memory (RRAM) Array for Neuromorphic Computing,,” IEEE Electron Device Letters, vol. 42, pp. 1168-1171, 2021.