現今工業界正朝著「微小化」的趨勢向前邁進，而奈米技術正是電子元件及電機系統未來繼續發展的基礎，因此從巨觀的元件演變到奈米電子元件是非常關鍵的過程，尤其是現今的45奈米甚至是22奈米世代更顯重要，原因為元件微小化的優點為性能提升及降低消耗功率，也就是說Vdd降低，當scaling到Vt不能再小時勢必也造成Vdd無法再小，問題就是發生在傳統的MOSFET的subthreshold swing最小的物理極限為60mV/dec.，故若能發展新型元件低於60mV/dec，便可解決此問題，穿隧場效電晶體(Tunneling FET)渴望為此問題找到解答，p/i/n操作在reverse bias利用band to band tunneling，可將subthreshold swing降到60mV/dec以下。
由於記憶體發展的趨勢為高密度、低耗能，而控制電晶體(一般來說是MOSFET)當需要減少元件的大小的時候將面臨問題，平面MOSFET的問題將妨礙記憶體的發展，因此考慮將平面結構發展成三維堆積的結構，而為能適用於雙極性記憶體 (如RRAM) 的使用，則因其寫入及抹除屬不同極性，故需發展雙向型控制單元，類似雙極性載子電晶體 (BJT) 之n/p/n或p/n/p結構，第四章節考慮採用n/p/n接面之雙極性二極體 ( bi-directional diode )期待此選擇器與RRAM記憶體結合，將可提高此二極體的功能性及實用性，可成為未來高密度之3D非揮發性記憶體之控制單元。

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