本論文將三角積分調變技術使用於極座標發射機中的封包調變上，並提出一個二階四位元全數位低通三角積分調變器，對其回授係數與輸入振幅大小做優化後，使得頻帶外雜訊低於一般的三角積分調變器，並讓發射機後端的帶通濾波器規格能夠減輕。當頻帶外雜訊降低後，發射機對於其他頻段的干擾可更為降低。

為了提升操作速率，本論文將高精確度截去器之判斷邏輯簡化，並利用查表法直接輸出回授數值，移除回授路徑上的移位乘法器。第二級迴路使用並列加法，透過改變加法順序使得第二級迴路可以減少一個加法器的延遲時間。簡化這些邏輯後，在使用CMOS 0.18μm製程所製造的晶片，其操作速率可至少達到208MHz。本論文以CMOS 0.18μm技術與CMOS 90nm技術各實現一個數位封包三角積分調變器，並可以處理第二代/第三代/第四代通訊系統之封包訊號，提供多重模式極座標發射機在封包調變的通用解決方案。而這兩顆晶片操作在208MHz時的消耗功率分別為3.582mW與0.99mW，在整個收發機中所佔的比率極低。

為了驗證本論文所提出的封包三角積分調變器的可行性，以本論文所設計的
三角積分調變器與切換式功率放大器陣列所組成的極座標發射機雛型也被實現。以CDMA-2000系統之訊號量測此發射機雛型時，輸出之鄰近通道功率洩漏比分別為-42.27dB與-54.02dB。以頻寬5MHz的LTE系統訊號量測時，輸出之鄰近通道功率洩漏分別為-34.12dB、-39.33dB與-32.36dB。在沒有附加的濾波器下，量測結果顯示此極座標發射機雛型能夠符合CDMA-2000與LTE(頻寬5MHz)規格，證明了本論文所提出之封包三角積分調變器應用在極座標發射機中的可行性。

In this thesis, a second-order, four-bit, all-digital lowpass delta-sigma (ΔΣ) modulator for envelope modulation in polar-transmitters is presented. In the proposed ΔΣ modulator, coefficients of feedback loops and input amplitude are optimized to lower out-of band noise band. With the proposed ΔΣ modulator, the out-of-band noise can be lower than conventional ΔΣ modulator. It's beneficial for easier the specification of the post bandpass filter in transmitters. Moreover, lower modulation noise reduced the interference which affect to other channel.

For high-speed operation, a high accurate truncator with simplified comparison logic is proposed, and multipliers for performance feedback coefficients are replaced by a look-up table. Delay time of the second-order loop is decreased one adder’s delay by parallel addition. This thesis had been demonstrated two of all-digital ΔΣ modulator which are fabricated by CMOS 0.18μm technology and CMOS 90nm technology. The chip which is fabricated by CMOS 0.18μm technology can operate at least to 208MHz thanks to logic simplification in the foregoing. These modulators can process envelope signals of 2G/3G/4G communication systems and provide a general envelope processing solution for multi-mode polar-transmitters. Power dissipation of two modulators is 3.582mW and 0.99mW, respectively. The power dissipation of envelope ΔΣ modulator is slight portion in transceivers.

In order to verify the feasibility of polar-transmitters using ΔΣ modulator which is proposed by this thesis, the prototype of polar-transmitter is assembled by the ΔΣ modulator and the switching power amplifier array. While the prototype polar-transmitter is measured with CDMA-2000 signal, adjacent channel leakage power ratios (ACLR) are -42.27dB and -54.02dB, respectively. While the input signal is LTE (Channel BW = 5MHz), ACLRs are -34.12dB,-39.33dB, and -32.36dB, respectively. The measurement result shows the prototype polar-transmitter can achieved CDMA-2000 and LTE (Channel BW = 5MHz) standard without additional filters and proved the feasibility of the envelope ΔΣ modulator which is proposed by this thesis.

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