研究生: |
劉興驊 Liu, Hsing-Hua |
---|---|
論文名稱: |
可見光眼動儀虹膜匹配系統硬體架構設計 Hardware Engine of Limbus Circle Matching for Visible-Spectrum Gaze Tracker |
指導教授: |
高文忠
Kao, Wen-Chung |
口試委員: |
林政宏
Lin, Cheng-Hung 范育成 Fan, Yu-Cheng 高文忠 Kao, Wen-Chung |
口試日期: | 2024/01/22 |
學位類別: |
碩士 Master |
系所名稱: |
電機工程學系 Department of Electrical Engineering |
論文出版年: | 2024 |
畢業學年度: | 112 |
語文別: | 中文 |
論文頁數: | 52 |
中文關鍵詞: | 眼動儀 、虹膜匹配 、晶片架構 |
英文關鍵詞: | eye tracker, limbus circle matching, hardware engine |
研究方法: | 實驗設計法 、 比較研究 |
DOI URL: | http://doi.org/10.6345/NTNU202400278 |
論文種類: | 學術論文 |
相關次數: | 點閱:82 下載:4 |
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可見光眼動儀以虹膜定位作為判斷眼睛凝視方向的主要基準。相較於傳統紅外光眼動儀,可見光眼動儀無法在影像中找出完整的瞳孔位置,必須以虹膜邊界來估算瞳孔中心。然而,由於虹膜邊界可能被眼瞼遮蓋,因此需要仰賴可靠的眼球模型與虹膜邊界比對演算法來精確定位虹膜位置。
在過去的幾年中,研究團隊已提出一種有效率的階層式搜尋法,用於在眼睛照片中定位虹膜邊界,並據以估計視線方向。本論文以此演算法架構為基礎,提出了可見光眼動儀中虹膜匹配的晶片架構,使其能夠從照片的特定範圍中快速完成虹膜匹配。在可用硬體資源受限的情況下,巧妙運用平行計算與管線式處理,以提高本晶片的計算效率。並在FPGA上實作了此晶片架構,其效能與處理結果與多核心的電腦計算結果相近,成功實現即時處理的目標。
The visible-spectrum eye tracker relies on iris positioning as the main feature for determining the direction of gaze. In comparison to traditional infrared eye trackers, the visible-spectrum eye tracker cannot identify the complete pupil position in the image and must estimate the pupil center based on the limbus circle. However, since the limbus circle may be obscured by eyelids, it is necessary to build a reliable eyeball model and to implement a limbus circle matching algorithm for precise iris positioning.
Over the past few years, the research team has proposed an efficient hierarchical search method for locating the limbus circle in eye images and subsequently estimating the gaze direction. Building upon this algorithmic framework, this paper introduces a chip architecture for limbus circle matching in visible-spectrum eye trackers, enabling rapid limbus circle matching within specific regions of photos. To enhance computational efficiency within hardware resource constraints, parallel computing and pipeline processing are appropriately applied in the chip design. The proposed chip architecture has been implemented on an FPGA, demonstrating performance and processing results comparable to those of multi-core computer calculations and achieving real-time processing goals.
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