在本世紀中，薄膜電晶體(TFT)和積體電路(IC)已被廣泛地研發，以不同的結構應用在電子相關設計方面。在這些研究之中，熱管理技術在元件的製程及在驅動時必須被列入考慮並且是影響元件特性的關鍵點。熱累積效應將會導致元件製程的失敗及元件特性下降。因此我們提出熱效應改善方法並且利用ISE TCAD半導體模擬軟體得到相關溫度分布圖形來驗證。第一章我們先簡介非晶矽軟性薄膜電晶體的發展變化沿革以及近年來3D立體積體電路(3D-ICs)的不同製程，並進一步探討研究動機和論文架構。第二章利用ISE TCAD模擬來驗證非晶矽軟性薄膜電晶體結構中夾一層熱傳導層，如銅、鋁、鉬，在偏壓驅動時可有效的逸散熱並且降低元件的溫度。第三章我們首先提出在3D-IC的不同層元件之間的隔絕氧化層中加入一層銅作為熱傳導層的結構，接著再利用ISE TCAD模擬2D模型在雷射誘發磊晶成長(LEG)製程時的溫度分布圖形。第四章我們將提出金氧半場效電晶體(MOSFET)的製程研究，在此製程步驟中，微影技術(Lithography)僅定義一道光罩。最後介紹元件製作的相關儀器操作流程與原理說明，以及Via陣列光罩圖形的設計。第五章對本論文之研究做結論並且探討未來研究工作目標與展望。

In this century, thin film transistors (TFTs) and integrated circuits (ICs) have been developed extensively and used in many electronics applications and designs with a range of different structures. Among these research, thermal management would be considered and played a critical role when devices during operation or in fabrication process. Thermal accumulation effects may lead to failure in manufacturing process and devices performance degradation. Therefore, we propose thermal improvement for these conditions and utilize ISE TCAD simulation to obtain the temperature distribution and profile. In chapter 1, we first introduce the course of change and development for flexible a-Si:H thin-film transistor and recent three-dimensional integrated circuits (3D-ICs) fabrication. Furthermore, motivation and organization of thesis will be explored. In chapter 2, we utilize TCAD simulation to verify that flexible a-Si:H TFT with thermal conduction layer such as copper (Cu), aluminum (Al), molybdenum (Mo) can efficient to dissipate more heat and lower device temperature during bias stress operation. In chapter 3, we first propose one structure, which has a thermal conduction layer such as Cu in ILD oxide layer for monolithic 3D-ICs. Then TCAD simulation was performed by solving the temperature distribution for 2D model during laser-induced epitaxial growth (LEG) process. In chapter 4, we make a description of fabrication process for Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) by lithography technique with only one mask definition. The operating instructions, principle of related instruments and design of mask pattern for Via arrays also be later summarized. In chapter 5, at the end of this thesis, we will make conclusions and future works.

References

[1] P. G. Lecomber, W. E. Spear, and A. Ghaith, “Amorphous-Silicon Field-Effect Device and Possible Application,” Electronics Letters, vol.15, no.6, pp.179–181, March, 1979.
[2] M. J. Powell. “The physics of amorphous silicon thin-film transistors,” IEEE Transactions on Electron Devices, vol.36, pp.2753–2763, 1989.
[3] D. M. Moffatt, “Glass Substrates for Flat-Panel Displays,” MRS Bulletin, vol.21, pp. 31–34, 1996.
[4] S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt and T. W. Sigmon, “PolySilicon Thin Film Transistors Fabricated at 100°C on a Flexible Plastic Substrate,” IEDM Digest of Technical Digest, pp.260, 1998.
[5] K. Long, A. Z. Kattamis, I.-C. Cheng, H. Gleskova, S. Wanger and J. C. Sturm, “Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250°C to 280°C,” IEEE Electron Device Letters, pp.111–113, 2006.
[6] M.-C. Lee, S.-M. Han, S.-H. Kang, M.-Y. Shin and M.-K. Han, “Poly-Si TFT Fabricated at 150°C Using ICP-CVD and Excimer Laser Annealing for Plastic Substrates,” IEDM Digest of Technical Digest, pp.215, 2003.
[7] J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif and J. D. Meindl, “Interconnect Limits on Gigascale Integration (GSI) in the 21st century,” Proceedings of IEEE, vol.89, pp.305, 2001.
[8] B. Rajendran, S. H. Jain1, T. A. Kramer and R. F. W. Pease, “Thermal Simulation of Laser Annealing for 3D Integration,” VLSI Multilevel Interconnection Conference (VMIC), 2003.
[9] B. Charlet, L. Di Cioccio and P. Leduc, “Enabling technologies for 3D System on Chip (SoC) integration and examples of 3D integrated structures,” Integrated Circuit Design and Technology (ICICDT), pp.1, 2007.
[10] K. Yamki, Y. Itoh, A. Wada, K. Morimoto and Y. Tomita, “4-Layer 3-D IC Technologies For Parallel Signal Processing,” IEDM Digest of Technical Digest, pp.599–602, 1990.
[11] Victor W. C. Chan, Philip C. H. Chan and Mansun Chan, “Three Dimensional CMOS Integrated Circuits on Large Grain Polysilicon Films,” IEDM Digest of Technical Digest, pp.161, 2000.
[12] Yong-Hoon Son, Jong-Wook Lee, Pilkyu Kang, Min-Gu Kang, Jin Bum Kim, Seung Hoon Lee, Young-Pil Kim, In Soo Jung, Byeong Chan Lee, Si Young Choi, U-In Chung, Joo Tea Moon and Byung-Il Ryu, “Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity,” Symposium on VLSI Technology Digest of Technical Papers, pp.80, 2007.
[13] Seong-Dong Kim, Cheol-Min Park and Woo. J.C.S, “Advanced Source/Drain Engineering for Box-Shaped Ultra shallow Junction Formation Using Laser Annealing and Pre-Amorphization Implantation in Sub-100-nm SOI CMOS,” IEEE Transactions on Electron Devices, vol. 49, no.10, pp.1748–1754, 2002.
[14] K. Yamazaki, Y. Itoh, A. Wada, K. Morimoto and Y. Tomita, Extended Abstracts of the 17th CSSDM (Tokyo), pp.155, 1985.
[15] K. Yamazaki, M. Yoneda, S. Ogawa, M. Ueda, S. Akiyama and Y. Terui, “Fabrication Technologies for Dual 4-kbit stacked SRAM,” IEDM Digest of Technical Digest, pp.435, 1986.
[16] R. Chatterjee, M. Fayolle, P. Leduc, S. Pozder, B. Jones, E. Acosta, B. Charlet, T. Enot, M. Heitzmann, M. Zussy, A. Roman, O. Louveau, S. Maitrejean, D. Louis, N. Kernevez, N. Sillon, G. Passemard, V. Po, V. Mathew, S. Garcia, T. Sparks and Zhihong Huang, International Interconnect Technology Conference (IITC), pp.81, 2007.
[17] N. Attaf, M. S. Aida and L. Hadjeris, “Thermal conductivity of hydrogenated amorphous silicon,” Solid State Communications, vol.120, pp.525–530, 2001.
[18] B. Rajendran, R. S. Shenoy, D. J. Witte, N. S. Chokshi, R. L. De Leon, G. S. Tompa and R. Fabian, “Low Thermal Budget Processing for Sequential 3-D IC Fabrication,” IEEE Transactions on Electron Devices, vol.54, no.4, pp.707, 2007.
[19] Yue Kuo, “Thin Film Transistors Materials and Processes,” vol.1, Amorphous Silicon Thin Film Transistors.
[20] M. H. Lee, K.-Y. Ho, P.-C. Chen, C.-C. Cheng, S. T. Chang, M. Tang, M. H. Liao and Y.-H. Yeh, “Promising a-Si:H TFTs with High Mechanical Reliability for Flexible Display,” IEDM Digest of Technical Digest, pp.299, 2006.
[21] J. G. Shaw and M. Hack, “An analytical model for calculating trapped charge in amorphous silicon,” Journal of Applied Physics, vol. 64, issue 9, pp.4562, 1988.
[22] G. Wachutka, “An extended thermodynamic model for the simultaneous simulation of the thermal and electrical behavior of semiconductor devices,” in Proceedings of the Sixth International NASECODE Conference (J. J. H. Miller, ed.), Boole Press Ltd., pp. 409–414, 1989.
[23] H. B. Callen, Thermodynamics and an Introduction to Thermostatistics. New York: John Wiley & Sons, 1985.
[24] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A Physically Based Mobility Model for Numerical Simulation of Nonplanar Devices,” IEEE Transactions on CAD, vol.7, no.11, pp.1164–1171, 1988.
[25] D. Kendall. presented at the Conf. Physics and Application of Lithium Diffused Silicon, NASA, Goddard Space Flight Center, December, 1969.
[26] J. G. Fossum, “Computer-aided numerical analysis of Silicon solar cells,” Solid-State Electronics, vol.19, pp.269–277, 1976.
[27] J. G. Fossum and D. S. Lee, “A physical model for the dependence of carrier lifetime on doping density in nondegenerate Silicon,” Solid-State Electronics, vol.25, no.8, pp.741–747, 1982.
[28] J. G. Fossum, R. P. Mertens, D. S. Lee, and J. F. Nijs, “Carrier recombination and lifetime in highly doped Silicon,” Solid-State Electronics, vol.26, no.6, pp.569–576, 1983.
[29] L. Huldt, N. G. Nilsson, and K. G. Svantesson, “The temperature dependence of band-to-band Auger recombination in silicon,” Applied Physics Letters, vol.35, no.10, pp.776, 1979
[30] W. Lochmann and A. Haug, “Phonon-assisted Auger recombination in Si with direct calculation of the overlap integrals,” Solid-State Communications, vol.35, pp.553–556, 1980.
[31] R. Häcker and A. Hangleiter, “Intrinsic upper limits of the carrier lifetime in silicon,” Journal of Applied Physics, vol.75, pp.7570–7572, 1994.
[32] A. Schenk, “Rigorous theory and simplified model of the band-to-band tunneling in Silicon,” Solid-State Electronics, vol.36, no.1, pp.19–34, 1993.
[33] Z. Suo, E. Y. Ma, H. Gleskova and S. Wanger, “Mechanics of Rollable and Foldable Film-on-foil Electronics,” Applied Physics Letters, vol.74, pp.1177, 1999.
[34] A. Sazonov and A. Nathan, “120 °C Fabrication Technology for a-Si:H Thin Film Transistors on Flexible Polyimide Substrates,” Journal of Vacuum Science & Technology A, vol.18, pp.780, 2000.
[35] V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three dimensional CMOS integrated circuit on large grain polysilicon films,” IEDM Digest of Technical Digest, pp.161–164, 2000.
[36] Patrick Wilkerson, Ashok Raman, Marek Turowski, “Fast, Automated Thermal Simulation of Three-Dimensional Integrated Circuits,” Inter Society Conference on Thermal Phenomena, pp.706–713, 2004.
[37] C. L. Chen, C. K. Chen, J. A. Burns, D.-R. Yost, K. Warner, J. M. Knecht, P. W. Wyatt, D. A. Shibles and C. L. Keast, “Thermal Effects of Three Dimensional Integrated Circuit Stacks,” IEEE International SOI Conference Proceedings, pp.91–92, 2007.
[38] Ting-Yen Chiang, S. J. Souri, Chi On Chui, K. C. Saraswat, “Thermal Analysis of Heterogeneous 3-D Ics with Various Integration Scenarios,” IEDM Digest of Technical Digest, pp.681–684, 2001.
[39] K. Rajkanan, R. Singh, and J. Shewchun, “Absorption Coefficient Of Silicon For Solar Cell Calculations,” Solid-State Electronics, vol.22, pp.793–795, 1979.
[40] Mitsuo Inoue, Hidetada Tokioka and Shinsuke Yura, “Method of fabricating a polycrystalline film by crystallizing an amorphous film with laser light,” United States Patent, no.7179725, pp.11, 2007.
[41] M. Smith, R. McMahon, M. Voelskow, D. Panknin and W. Skorupa, “Modeling of flash-lamp-induced crystallization of amorphous silicon thin film on glass,” Journal of Crystal Growth, pp.249–260, 2005.
[42] Hideaki Kuroda, “Method of manufacturing a semiconductor device having a memory cell and peripheral circuit including forming a first electrode for the capacitor,” United States Patent, no.5346843, pp.3, 1994.
[43] Yoichi Akasaka, “Three-Dimensional IC Trends,” Proceedings of IEEE, vol.74, no.12, pp.1703–1714, 1986.
[44] Yoichi Akasaka and Tadashi Nishimura, “Concept and basic technologies for 3-D IC structure,” IEDM Digest of Technical Digest, pp.488–491, 1986.
[45] Ryoichi Ishihara, Vikas Rana, Ming He, Wim Metselaar and Kees Beenakker, “Single-Grain Si TFTs and Circuits for Flexible Electronics and 3D-ICs,” The 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp.174–177, 2006.