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研究生: 林鈺庭
Lin, Yu-Ting
論文名稱: 具有誤差回授架構的低功耗三階雜訊移頻逐次逼近式類比數位轉換器
A Low-Power Third-Order Noise-Shaping SAR ADC with an Error Feedback Architecture
指導教授: 郭建宏
KUO, Chien-Hung
口試委員: 郭建宏
KUO, Chien-Hung
陳建中
Chen, Jiann-Jong
黃育賢
Hwang, Yuh-Shyan
口試日期: 2025/01/03
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2025
畢業學年度: 113
語文別: 中文
論文頁數: 63
中文關鍵詞: 誤差回授雜訊移頻逐次逼近暫存式類比數位轉換器互補自偏壓差分放大器接成的單位增益緩衝器單位增益緩衝器低功耗
英文關鍵詞: Error-feedback, Noise-shaping SAR ADC, CSDA, Unity gain buffer, Low Power
研究方法: 實驗設計法
論文種類: 學術論文
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  • 在現代數位電子裝置中,類比數位轉換器扮演著至關重要的角色。它們廣泛應用於各種領域,包括通訊、醫療設備、工業控制、儀器儀表和消費性電子產品等。隨著科技無止盡的發展和應用的擴大,對低功耗、高精度和面積小類比數位轉換器的需求也日益增長,因此,我們將以提高效能為目標來設計類比數位轉換器。本文提出了一個具有誤差回授架構的低功耗三階雜訊移頻逐次逼近式類比數位轉換器。此電路僅用一顆單位增益緩衝器,有效減少整體的功率消耗與面積成本。所使用的單位增益緩衝器採用了互補自偏壓差分放大器接成的單位增益緩衝器,不需額外的共模回授和偏壓電路。此外,由於所提出的架構採用單位增益緩衝器和以乒乓式操作的延遲元件來傳遞量化誤差,無需考慮電容之間的匹配程度。與傳統的積分器比較起來,會有較佳的訊號準確度。此電路採用TSMC 0.18-μm 1P6M CMOS製程技術製作,所實現的晶片核心面積為0.417×0.669 mm2。此電路在2-MHz的取樣頻率及20-kHz的頻寬下,測得的最佳SNDR值為85.17 dB,相當於13.86-bit的ENOB。所提出的ADC在1.8-V電源電壓下的功率消耗為75.5 μW。FoMs為169.43 dB,FoMw為126.53 fj/Conv.。

    In modern digital electronic devices, analog-to-digital converters (ADCs) play a crucial role. They find widespread use in numerous sectors, including communications, medical equipment, industrial control, instrumentation, and consumer electronics. With advancing technology and expanding application areas, there is an increasing demand for ADCs that are low power, high precision, and compact. Therefore, we aim to enhance ADCs focusing on low power consumption, high precision, and small footprint.This paper presents a low-power third-order noise-shaping SAR ADC with an error feedback architecture. The circuit uses only one unity-gain buffer, effectively reduce overall power consumption and area cost. The employed unity-gain buffer is a complementary self-biased differential amplifier (CSDA), eliminating the need for additional common-mode feedback and bias circuits. Moreover, since the proposed architecture employs unity gain buffers and delay elements operating in a ping-pong manner to deliver the quantization error, there is no need to consider the matching degree between capacitors. Compare with traditional integrators, there will be better signal accuracy.The proposed ADC fabricated in TSMC’s 0.18-μm 1P6M CMOS process technology, with a chip core area of 0.417×0.669 mm². It achieves an optimal SNDR of 85.17 dB at a sampling frequency of 2 MHz and a bandwidth of 20 kHz, corresponding to an ENOB of 13.86-bits. The power consumption of the proposed ADC at a 1.8-V supply voltage is 75.5 μW. The FoMs is 169.43 dB, and the FoMw is 126.53 fj/Conv..

    致   謝 i 摘   要 iii ABSTRACT iv 目   錄 v 表 目 錄 viii 圖 目 錄 ix 第一章  緒論 1 1.1  研究動機 1 1.2  積體電路設計流程 2 1.3  論文大綱與概要 3 第二章  類比數位轉換器概論 4 2.1  前言 4 2.2  效能指標 5 2.2.1  訊號雜訊比 5 2.2.2  訊號雜訊失真比 5 2.2.3  有效位元數 6 2.2.4  動態範圍 6 2.2.5  無雜散動態範圍 7 2.2.6  品質因數 7 2.3  量化器 7 2.3.1  單位元量化器 8 2.3.2  多位元量化器 8 2.3.3  量化誤差 10 2.4 超取樣率 11 2.5 雜訊移頻 12 2.6  逐次逼近式類比數位轉換器 13 2.6.1  二分搜尋演算法 14 2.6.2  SAR ADC運作流程 15 第三章  基本電路元件設計 16 3.1  前言 16 3.2  交換電容式電路 16 3.3  開關 16 3.3.1  NMOS開關和PMOS開關 17 3.3.2  傳輸閘開關 17 3.3.3  靴帶式開關 18 3.4  單位增益緩衝器 18 3.5  動態比較器 19 3.6  電位移轉換器 20 3.7  真單相位時脈電路 21 3.8  逐次逼近式暫存器 22 3.9  分開電容型電容式回授電路 23 3.10  數位類比轉換器邏輯電路 23 第四章  使用EF結構的三階NS SAR類比數位轉換器 26 4.1  前言 26 4.2  使用誤差回授結構的三階雜訊移頻架構 27 4.3  電路非理想效應 29 4.3.1  熱雜訊 30 4.3.2  時脈抖動 31 4.3.3  運算放大器之有限增益 32 4.4  MATLAB線性模型模擬 32 4.5  電路穩定性 35 4.6  電路架構 36 4.6.1  乒乓式切換延遲電路 37 4.6.2  降低時鐘串擾的電容穩定化方法 38 4.6.3  整體電路架構 39 4.6.4  電路模擬結果 44 4.7  電路佈局與實現 46 4.8  晶片量測 50 4.8.1  輸入終端電路 52 4.8.2  供應電壓電路 53 4.8.3  濾波槽電路 53 4.8.4  晶片量測環境 54 4.8.5  量測結果 54 第五章  總結與未來展望 56 5.1  總結 56 5.2  未來展望 57 參 考 文 獻 59 自     傳 62 學 術 成 就 63

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