研究生: |
羅俊道 |
---|---|
論文名稱: |
可應用於非揮發性記憶體具穿隧機制之交錯型選擇器開發 The Cross-Bar Selector Development of Tunneling Mechanism for Non-Volatile Memory Applications |
指導教授: | 李敏鴻 |
學位類別: |
碩士 Master |
系所名稱: |
光電工程研究所 Graduate Institute of Electro-Optical Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 98 |
中文關鍵詞: | Cross-point記憶體 、穿隧式雙向選擇器 、電阻式記憶體 、穿隧機制 |
英文關鍵詞: | cross-point memory, Tenneling Bi-directional Switch, MIM, RRAM |
論文種類: | 學術論文 |
相關次數: | 點閱:158 下載:0 |
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Cross-point記憶體開關來整合於RRAM中,由於記憶體發展的趨勢是往高密度且低耗能的方向,欲配合Bipolar-RRAM(雙向電阻式記憶體)的製程及操作相容性,此selector/switch需採雙向操作模式,而MIM雙向性特性及結構製程條件,使其能廣泛的應用在Cross-point記憶體結構中。
而本次的研究成果,TiN-TaOx-TiO2-TaOx-TiN結構,只要面積可達10-10cm2以上,電流密度就可達到107 A/cm2以上。TiN-Al2O3-HfO2-Al2O3-TiN結構已可達104以上的access ratio (Von/(1/2) Von),而TiN-Al2O3-TiO2-Al2O3-TiN的access ratio也可達103以上。在本次研究過程中,TiN-TaOx-TiO2-TaOx-TiN在小面積小偏壓下是以普爾-法蘭克效應、蕭基發射為主的傳輸機制。在TiN-Al2O3-HfO2-Al2O3-TiN結構中,電流有兩段式機制,定義在轉折處為VT,在V<VT時,是以普爾-法蘭克效應為主,而在V>VT時,則包含了普爾-法蘭克效應、蕭基發射及穿隧機制,此結構為熱電子放射機制。而TiN-Al2O3-TiO2-Al2O3-TiN結構亦也有兩段式電流機制,在V>VT或V<VT,皆以普爾-法蘭克效應及穿隧機制為主,在小偏壓下以穿隧機制,而在大偏壓下可能還會加入熱電子放射的機制。而且本此研究的優勢在於無使用到任何貴重金屬如Pt, Au…,且無磁性材料如BaTiO3…,製程整合對於量產與高密度多層堆疊製程整合都是一大優勢。
未來目標則是與RRAM整合以提高功能性及實用性,可成為未來高密度之3D非揮發性記憶體之控制單元。
In order to develop the 1S1R in cross-point structure, the requirements of the selector are high current density and high access ratio to avoid sneak current path effect for multi-stack array. Furthermore, the reliability of the selector in cross-point array was discussed. In this paper, we focus on VBS (Varistor Bi-directional Switch) development.
For TiN-TaOx-TiO2-TaOx-TiN, we have maximum current density 107 A/cm2, the small bias is attributed Poole-Frenkel emission and Schottky emission, respectively. For TiN-Al2O3-HfO2-Al2O3-TiN, we have maximum access ratio (Von/(1/2) Von) ~104, the small bias is attributed Poole-Frenkel emission, and the larger bias is attributed Poole-Frenkel emission, Schottky emission and tunneling, respectively. For TiN-Al2O3-TiO2-Al2O3-TiN, we have maximum access ratio ~103, the small and larger bias are attributed F-N tunneling and Schottky emission, respectively. The bi-selectors without using noble and magnetic materials show the scaling feasibility due to its inert property to SiO2 encapsulation.
Besides, the selector with higher current density and access ratio will be developed in this project. We plan to design high/low/high bandgap to approach the target with high density stack, high capacity, low power consumption, and cost down. The preparing development MIM with spec. for switch device of bi-direction diode, and avoid the MOSFET process. The stackable memory with selector has the advantage of 3D structure, and avoids transistor fabrication process. It has the opportunity to be the leader of the high density stackable memory – stack cross-point NVM.
[1] Pirovano, L. Lacaita , F. Pellizzer, A. Kostylev, A. Benvenuti, and R.Bez,“Low-Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials, ” IEEE Trans. Electron Devices,, vol. 51, no.5, pp. 714-719, 2004.
[2] O. Auciello, “Science and Technology of Thin Films and Interfacial Layers in Ferroelectric and High-dielectric Constant Hterostructures and Application to Devices, ” Journal of Applied Physics, vol. 100, issue. 5, p. 051614, 2006.
[3] A. Sawa, “ Resistive Switching in Metal Oxides, ” Material Today, vol. 11, no.6, pp. 28-36, 2008.
[4] J. Liang, and H.S.P. Wong, “Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies, ” IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2531 - 2538, 2010.
[5] F. Pellizzer, A. Benvenuti, B. Gleixner, Y. Kim, B. Johnson, M. Magistretti, T. Marangon, A. Pirovano, R. Bez, and G. Atwood, “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications,” in Symp. on VLSI Tech. Dig., pp. 80-81, 2006.
[6] B. Cho, T.W. Kim, S. Song, Y. Ji, M. Jo, H. Hwang, G.Y. Jung, and T. Lee, “Rewritable Switching of One Diode–One Resisto Nonvolatile Organic Memory Devices, ” Adv. Mater,vol.22,pp.1228-1232, 2010.
[7] J. Shin, G. Choi, J. Woo, J. Park, S. Park, W. Lee, S. Kim, M. Son, and H. Hwang, “MIM-type cell selector for high-density and low-power cross-point memory application,” Microelectronic Engineering, 93, p. 81-84, 2012.
[8] J. Shin, I. Kim, K.P. Biju, M. Jo, J. Park, J. Lee, S. Jung, W. Lee, S. Kim, S. Park, and H. Hwang, “TiO2-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application,” Journal of Applied Physics, vol. 109, issue. 3, pp. 033712, 2011.
[9] Y.Y. Chen, L. Goux, S. Clima, B. Govoreanu, R. Degraeve, G.S.Kar, A. Fantini, G. Groeseneken, D.J. Wouters, and M. Jurczak, “Endurance/Retention Trade-off on HfO2/Metal Cap 1T1R Bipolar RRAM,” IEEE Trans. Electron Devices,vol. 60, no. 3, pp. 1114-1120, 2013.
[10] M.C. Wu, Y.W. Lin, W.Y. Jang, C.H. Lin, and T.Y. Tseng, “Low-Power and Highly Reliable Multilevel Operation in ZrO2 1T1R RRAM,” IEEE Electron Device Lett., vol. 32, no. 8,pp.1026-1028, 2011.
[11] X. P. Wang, Z. Fang, X. Li, B. Chen, B. Gao, J. F. Kang, Z. X. Chen, A. Kamath, N. S. Shen, N. Singh, G. Q. Lo, and D. L. Kwong, “Highly Compact 1T-1R Architecture (4F2 Footprint) Involving Fully CMOS Compatible Vertical GAA Nano-Pillar Transistors and Oxide-Based RRAM Cells Exhibiting Excellent NVM Properties and Ultra-Low Power Operation,” in IEDM Tech. Dig., pp. 493-494, 2012.
[12] T. Li , et al , US.Patent NO: 2009/0032817.
[13] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, and M.-J. Tsai, ”Low Power and High Speed Bipolar Switchingwith A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM, ” in IEDM Tech. Dig., p. 297, 2008.
[14] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin, W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, and M.-J. Tsai,” Highly Scalable Hafnium Oxide Memory with Improvements of Resistive Distribution and Read Disturb Immunity,” in IEDM Tech. Dig., p. 105, 2009.
[15] E. Linn, R. Rosezin, C. Kügeler, and R. Waser , “Complementary resistive switches for passive nanocrossbar memories,” NATURE MATERIALS ,VOL 9,pp.403-406,2010.
[16] 楊濟綸, “應用於多層堆疊之交錯型非揮發性記憶體選擇器,” 臺灣師範大學碩士論文,2012.
[17] J.J. Huang, Y.M. Tseng, W.C. Luo, C.W. Hsu, and T.H. Hou,” One Selector-One Resistor (1S1R) Crossbar Array for High-density Flexible Memory Applications,” in IEDM Tech. Dig., pp. 733-736, 2011.
[18] J.J. Huang, T.H. Hou, C.W. Hsu, Y.M. Tseng, W.H. Chang, W.Y. Jang, and C.H. Lin ,” Flexible One Diode–One Resistor Crossbar Resistive-Switching Memory,” Japanese Journal of Applied Physics,vol.51,2012
[19] C.L. Lo, T.H. Hou, M.C. Chen, and J.J. Huang ,” Dependence of Read Margin on Pull-Up Schemes in High-Density One Selector–One Resistor Crossbar Array,” IEEE Trans. Electron Devices,vol. 60, no. 1, pp.420-426,2013
[20] J.H. Oh, J.H. Park, Y.S. Lim, H.S. Lim, Y.T. Oh, J.S. Kim, J.M. Shin, J.H. Park, Y.J. Song, K.C. Ryoo, D.W. Lim, S.S. Park, J.I. Kim, J.H. Kim, J. Yu, F. Yeung, C.W. Jeong, J.H. Kong, D.H. Kang, G.H. Koh, G.T. Jeong, H.S. Jeong, and Kinam Kim , “Full Integration of Highly Manufacturable 512Mb PRAM based on 90nmTechnology ,” in IEDM Tech. Dig., 2006.
[21] Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong , “An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory,” in Symp. on VLSI Tech. Dig., 2007.
[22] F. Pellizzer, A. Benvenuti, B. Gleixner, Y. Kim, B. Johnson, M. Magistretti, T. Marangon, A. Pirovano, R. Bez, and G. Atwood, “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications,” in Symp. on VLSI Tech. Dig.,2007.
[23] M.J. Lee, Y. Park, B.S. Kang, S.E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.H. Lee, S.J. Chung, Y.H. Kim, C.S. Lee, J. BongPark, I.G. Baek, and I.K. Yoo, “2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications,” in IEDM Tech. Dig.,2007.
[24] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine,A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura, and K. Torii, “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode,” in Symp. on VLSI Tech. Dig., 2009.
[25] M. H. Lee, C.-Y. Kao, C.-L. Yang, Y.-S. Chen, H. Y. Lee, F. Chen, and M.-J. Tsai, “Reliability of ambipolar switching poly-Si diodes for crosspoint memory applications,” in Proc. 69th Annu. Device Res. Conf., pp89-90,2011.
[26] S. S. Sheu, P. C. Chiang, W. P. Lin, H. Y. Lee, P. S. Chen, Y. S. Chen, T. Y. Wu, F. T. Chen, K. L. Su, M. J. Kao, K. H. Cheng , and M. J. Tsai, “A 5ns Fast Write Multi-Level Non-Volatile 1 K bits RRAM Memory with Advance Write Scheme,” in Symp. on VLSI Tech. Dig., 2009.
[27] J. J. Huang, Y. M. Tseng, C. W. Hsu, and T. H. Hou, “Bipolar Nonlinear Ni/TiO2/Ni Selector for 1S1R Crossbar Array Applications,” IEEE Electron Device Lett.,vol. 32, no. 10, pp.1427-1429, 2011.
[28] W. Lee, J. Park, J. Shin, J. Woo, S. Kim, G. Choi, S. Jung, S. Park, D. Lee, E. Cha, H. Dong Lee, S.G. Kim, S. Chung and H.Hwang,“Varistor-type Bidirectional Switch (JMAX>107A/cm2, Selectivity~104) for 3D Bipolar Resistive Memory Arrays,” in Symp. on VLSI Tech. Dig.,pp37-38,2012.
[29] V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and U. Ganguly,“Punchthrough-Diode-Based Bipolar RRAM Selector by Si Epitaxy,” IEEE Electron Device Lett., vol. 32, no. 10, pp. 1427–1429, Oct. 2011.
[30] C. H. Cheng, S. H. Lin, K. Y. Jhou, W. J. Chen, C. P. Chou, F. S. Yeh, J. Hu, M. Hwang, T. Arikado, S. P. McAlister, and Albert Chin, “High Density and Low Leakage Current in TiO2 MIM Capacitors Processed at 300C,” IEEE Electron Device Lett., vol. 29, no. 8, pp.845-847,2008.
[31] 李雅明, 固態電子學, 全華圖書出版社, p.414-434, 1997.
[32] S. M. Sze, Physics of Semiconductor Devices, John Wily & Sons, 2nd ed.,1981.
[33] R. Holm, “The Electric Tunnel Effect across Thin Insulator Films in Contacts,” Journal of Applied Physics, Vol.22 ,p.569, 1951.
[34] J. C. Fisher and I. Giaever, “Tunneling Through Thin Insulating Layers,” Journal of Applied Physics, Vol.32 ,p.172, 1961.
[35] K. H. Gundlach, “Zur Berechung des Tunnelstroms Durch Eine Trapzeformige Potentialstufe,” Solid-State Elecronics, Vol. 9, p. 949, 1966.
[36] J. Jung, and W.J. Cho, “Tunnel Barrier Engineering for Non-Volatile Memory,” Journal of Semiconductor Technology And Science, Vol. 8, no.1, pp.32-39 , 2008.
[37] K. K. Likharev, “Layered tunnel barriers for nonvolatile memory devices,” Applied Physics Letters, vol.73, no. 15,pp.2137-2139, 1998.
[38] W. Lee, J. Park, S. Kim, J. Woo, J. Shin, G. Choi, S. Park, D. Lee, E. Cha, B.H. Lee, and H. Hwang, “High Current Density and Nonlinearity Combination of Selection Device Based on TaOx/TiO2/TaOx Structure for One Selector One Resistor Arrays,” in ACSNANO, vol.6, no.9, pp. 8166–8172, 2012.
[39] B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. De Meyer, “VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices,” IEEE Electron Device Lett., vol. 24, no. 2, pp.99-101,2003.
[40] F. Driussi, S. Marcuzzi, P. Palestri, and L. Selmi, “Gate current in stacked dielectrics for advanced FLASH EEPROM cells”, Proceedings of ESSDERC, pp. 317-320, 2005.
[41] G. Jegert, A. Kersch, W. Weinreich,U. Schröder, and P. Lugli, “Modeling of leakage currents in high-_ dielectrics: Three-dimensional approach via kinetic Monte Carlo,” Applied Physics Letters, vol.96, no. 6,pp.062113, 2010.
[42] S. Yu, X. Guan, and H.-S. P. Wong,“Conduction mechanism of TiN/HfOx/Pt resistive switching memory: A trap- assisted-tunneling model,” Applied Physics Letters, vol.99, no. 6,pp. 063507, 2011.
[43] 陳建熹, “二氧化鉿─二氧化鈦複合薄膜於非揮發性電阻式記憶體之特性研究,” 國立清華大學碩士論文,2009.
[44] 王裕淵, “應用氮化矽/二氧化矽/氮化矽堆疊形成電致可調變穿隧能障之鍺量子點電晶體之研製,” 國立中央大學碩士論文, 2010.
[45] 馮俊傑, “氧化鎂薄膜應用在電阻式隨機存取記憶體之電性研究,”銘傳大學碩士論文,2011.
[46] 韓明恩, “界面氮氧化鉭氧化層對銅摻雜二氧化矽電阻切換性質的影響,” 國立台灣科技大學碩士論文,2011.
[47] 栗漢翔, “以氧化鋯和氧化鋯-氧化鎳薄膜為介電層進行單極式電阻切換研究,” 國立台灣科技大學碩士論文,2012