本論文旨在於FPGA(Field Programmable Gate Array)平台上實作菲涅爾轉換之硬體架構實現。
本系統透過增加硬體電路與SDRAM(Synchronous Dynamic Random Access Memory)之間存取資料的頻寬，以達到低面積及高速運算之目的。一般的硬體電路在做龐大的資料運算時，都會耗費相當多的時間與主記憶體做資料的存取，而以往的菲涅爾轉換之硬體電路並沒有充分的使用存取記憶體的資料頻寬，使得電路運算時間增加，而降低電路的效能。
本論文之硬體架構是使用主動型態的記憶體讀寫電路，該電路有效的利用SDRAM所提供的記憶體的資料頻寬，來增進存取記憶體的效能，降低整體運算過程中所耗費掉的時間，達到高速運算之目的。由於電路運算所需要的資料都存放於SDRAM之中，而不需要使用到On-Chip RAM，因此電路整體面積較小，達到低面積之目的。

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