隨著半導體製程的進步發展，Power, Performance, Area (PPA)三大指標是晶片設計最高原則，所有製程與晶片設計都圍繞著這三個指標，如今技術越來越進步，市場需求持續上升，為了滿足物聯網多裝置需求，同時又需要兼顧到全球暖化與環境保護的議題，低功耗與高效能的晶片不斷的推陳出新，高取樣率的電路被廣泛使用，低功耗的逐次逼近式類比數位轉換器為現在主流。

本論文為使用1.4V電源的三階三角積分調變器，採用自給式回授反向器做為雜訊移頻之積分器，優點為不需要額外的偏壓及回授電路，能降低功耗和節省佈局面積，三階CIFF低失真架構，各級積分器只需要處理雜訊，不包含輸入的電壓訊號，因此不需要高增益運算放大器，積分器能設計的較為節能以降低功耗，此外，為了降低開關的穿隧效應導致回授電壓不穩定，本文電路使用分裂電容，不僅能提高運算放大器的穩定性，更能減少一個電壓源輸入 (Vcm) 使用。本文之電路實踐採用 T18 0.18um 1P6M CMOS 製程，晶片面積為0.454mm2，此電路取樣頻率為2.56MHz，頻寬為20kHz時，最佳效能SNDR 81.09dB，SNR 81.61dB，ENOB 13.18bits，頻寬為10kHz時，最佳效能SNDR 86.24dB，SNR 87.31dB，ENOB 14.03bits。在1.4V供應電壓時消耗功率為125.9uW。

As semiconductor processes continue to advance, the three key factors of Power, Performance, and Area (PPA) have become the highest principles in IC design. All processes and chip designs revolve around these three indicators. With the continuous advancement of technology and the increasing market demand, the need to satisfy the requirements of multiple IoT devices while also addressing global warming and environmental protection issues has led to the continuous introduction of low-power and high-performance chips. High sampling rate circuits are widely used, and low-power Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) have become mainstream.
This paper presents a third-order delta-sigma modulator operating with a 1.4V power supply. The modulator employs a self-bias inverter as the integrator for noise shaping, which has the advantage of not requiring additional bias and feedback circuits, reducing power consumption and saving layout area. The third-order CIFF low-distortion architecture processes only noise in each stage integrator without including the input signal, which eliminates the need for high-gain operational amplifiers. Consequently, the integrators can be designed with lower power consumption to further reduce energy usage. Additionally, to mitigate feedback voltage instability caused by switch tunneling effects, this circuit adopts split capacitors, which not only enhance the operational amplifier's stability but also eliminate the need for an additional voltage source input (Vcm). The circuit implementation in this paper uses the T18 0.18µm 1P6M CMOS process, with a chip area of 0.454mm². The circuit's sampling frequency is 2.56 MHz, with a bandwidth of 20 kHz and 10kHz , achieving a maximum performance of SNDR 81.09 dB, 86.24dB, SNR 81.61 dB, 87.31dB and ENOB 13.18 bits, 14.03 bit, respectively. The power consumption at 1.4V supply voltage is 125.9 µW.

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