近年來因科技發展運算處理與記憶體的與日俱增，而VDD降低對於電子產品開發是相當重要的，俱鐵電效應之鉿鋯氧化物（Hafnium-based Oxides）閘極堆疊鐵電場效電晶體（Ferroelectric FET，FE-FET）有機會應用在降低次臨界擺幅（Subthreshold Swing）及記憶體使用，前者使VDD能夠再進一步的降低，後者提升鐵電記憶體殘餘極化（Remnant Polarization）量。
利用壓電響應顯微鏡（Piezoresponse Force Microscopy , PFM）驗證了鉿鋯氧化物(HfZrO2)中存在鐵電電滯曲線和極化引起的殘餘極化。並研究MFM（Metal–Ferroelectric–Metal）在不同下電極厚度的遲滯曲線改變，找出最佳化厚度。鐵電電晶體利用雷射退火使源/汲極活化，提升元件的ON-current，使得元件的運作速度更快。

Recently, ferroelectric technology has attracted a lot of attentions of CMOS and memory due to reduce VDD for a critical issue. Ferroelectric Hf-based oxide gate stack transistor has the opportunity to breakthrough the physical limitation of subthreshold swing (SS) and emerging memory application. The enhancement of Remnant Polarization is the direction for investigation in this work, as well as VDD to be further reduced.
PFM is verified the presence of ferroelectric hysteresis loop and remnant polarization in HfZrO2. This study focus on the hysteresis loop to optimize with different bottom electrode thicknesses of MFM capacitor. The ON-current of FeFET is obtained by utilizing laser annealing to activate the source/drain of FeFET, which has the opportunity to achieve high speed operation.

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