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研究生: 柯奇恩
KE,Chi-En
論文名稱: 多通道棘波分類系統之低功率ASIC電路設計
Efficient ASIC Architecture for Low-Power Multi-Channel Spike Sorting System
指導教授: 黃文吉
Hwang, Wen-Jyi
學位類別: 碩士
Master
系所名稱: 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 45
中文關鍵詞: 棘波分類棘波偵測特徵擷取特殊應用積體電路非線性能量運算子通用賀賓學習法則
英文關鍵詞: spike sorting, spike detection, feature extraction, ASIC, NEO, GHA
論文種類: 學術論文
相關次數: 點閱:152下載:1
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  • 本論文針對目前現有的棘波分類系統設計架構,並使用ASIC電路設計方式來實現此架構。本論文採用Nonlinear Energy Operator (NEO) 來偵測棘波,並搭配Generalized Hebbian Algorithm (GHA)演算法將偵測到的棘波進行特徵擷取。為了減少硬體資源的消耗,GHA架構中在計算調整不同組權重值時皆共享相同一塊計算電路。因此,本論文所提出的架構同時擁有較低的晶片面積,以即使用了台積電90奈米製程和對於功率消耗優化之技術,使得在功率消耗的這部分也有良好的表現。最後由於使用了多通道的訊號輸入,本論文在棘波分類系統的吞吐量能有大幅的提升。

    第一章 緒論 1 1.1 研究背景與動機目的 1 1.2 全文架構 5 第二章 棘波分類之基礎介紹與演算法則 6 2.1棘波分類的介紹 6 2.2 棘波偵測演算法則 8 2.3 特徵擷取演算法則 9 2.4 多通道棘波輸入 11 第三章 棘波分類系統架構 17 3.1 NEO單元 18 3.2 Spike Buffer單元 20 3.3 GHA單元 22 3.4 Global Controller 單元 28 3.5 Clock Gating技術於電路中之實作 30 第四章 實驗數據與效能分析 31 4.1 開發平台與實驗環境介紹 31 4.2 實驗數據呈現與討論 35 第五章 結論 42 參考文獻 43

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