研究生: |
柯奇恩 KE,Chi-En |
---|---|
論文名稱: |
多通道棘波分類系統之低功率ASIC電路設計 Efficient ASIC Architecture for Low-Power Multi-Channel Spike Sorting System |
指導教授: |
黃文吉
Hwang, Wen-Jyi |
學位類別: |
碩士 Master |
系所名稱: |
資訊工程學系 Department of Computer Science and Information Engineering |
論文出版年: | 2014 |
畢業學年度: | 102 |
語文別: | 中文 |
論文頁數: | 45 |
中文關鍵詞: | 棘波分類 、棘波偵測 、特徵擷取 、特殊應用積體電路 、非線性能量運算子 、通用賀賓學習法則 |
英文關鍵詞: | spike sorting, spike detection, feature extraction, ASIC, NEO, GHA |
論文種類: | 學術論文 |
相關次數: | 點閱:152 下載:1 |
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本論文針對目前現有的棘波分類系統設計架構,並使用ASIC電路設計方式來實現此架構。本論文採用Nonlinear Energy Operator (NEO) 來偵測棘波,並搭配Generalized Hebbian Algorithm (GHA)演算法將偵測到的棘波進行特徵擷取。為了減少硬體資源的消耗,GHA架構中在計算調整不同組權重值時皆共享相同一塊計算電路。因此,本論文所提出的架構同時擁有較低的晶片面積,以即使用了台積電90奈米製程和對於功率消耗優化之技術,使得在功率消耗的這部分也有良好的表現。最後由於使用了多通道的訊號輸入,本論文在棘波分類系統的吞吐量能有大幅的提升。
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