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研究生: 林聖淇
Lin, Sheng-Chi
論文名稱: 基於三角積分調變器之D類功率放大器
A Delta-Sigma Modulator-Based Class-D Amplifier
指導教授: 郭建宏
Kuo, Chien-Hung
學位類別: 碩士
Master
系所名稱: 電機工程學系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 132
中文關鍵詞: D類功率放大器開關放大器三角積分調變D類功率放大器
英文關鍵詞: Class-D Amplifier, Switching Amplifier, Delta- Sigma Class-D Amplifier
DOI URL: https://doi.org/10.6345/NTNU202202693
論文種類: 學術論文
相關次數: 點閱:132下載:0
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  • 隨著時間的進行,人們對生活品質的要求總是好還要更好,尤其是幾乎每個人每天都會隨身帶著的智慧型行動裝置更是日新月異,近年來發展的攜帶型行動裝置內部皆有一個功率放大器用以驅動內建的喇叭(Lout Speaker),而D類放大器能減少熱能的產生,且不需要散熱裝置,因此相較於A類與AB類功率放大器來說有著較好的轉換效率與較小的體積,符合了目前攜帶型行動裝置需要低耗電與小體積的趨勢。
    本論文之D類放大器採用一個新的架構,藉由2階3位元三角積分調變器之9位階數位輸出訊號產生控制D類功率放大級之控制訊號,運用較為簡單的控制方法,讓多位元的三角積分調變器也能順利控制D類功率放大器之功率放大級運作。最後則藉由回授來增加整體線性度。
    本論文使用TSMC 0.18 μm 1P6M 標準CMOS製程,供應電壓為1.8V與3V,系統頻寬為25 kHz,取樣頻率為2.56MHz,OSR為51.2,輸入訊號頻率為7.1875kHz,輸入訊號振幅為-13.86 dB,所得到之訊號雜訊比為78.5dB,THD為0.0095%,總消耗功率為145mW。

    A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 9-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78.5 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.0095% at a power consumption of 145 mW.

    目錄 摘要 I ABSTRACT III 致謝 V 目錄 VII 圖目錄 XII 表目錄 XVII 第一章 緒論 1 1.1 研究動機與背景 1 1.2 積體電路設計流程 2 第二章 功率放大器概論之效能指標與架構比較 5 2.1 功率放大器概論 5 2.2 功率放大器之應用 6 2.3 線性功率放大器之介紹 7 2.3.1 A類功率放大器 8 2.3.2 B類功率放大器 9 2.3.3 AB類功率放大器 10 2.4 非線性功率放大器之介紹 12 2.4.1 D類功率放大器 12 2.4.2 G類功率放大器 13 2.5 D類功率放大器 14 2.5.1 D類功率放大器之原理 14 2.5.2 功率放大級電路 15 2.6 D類功率放大器規格分析 19 2.6.1 效率 19 2.6.2 輸出功率 21 2.7 D類功率放大器之調變方法與架構 21 2.7.1 脈波寬度調變 21 2.7.2 三角積分調變 23 2.7.3 脈波密度調變 24 2.7.4 連續時間三角積分調變 24 2.7.5 多級脈波寬度調變 25 2.7.6 總結 26 2.8 章節結論 26 第三章 三角積分調變器 27 3.1 效能指標 27 3.1.1 訊號雜訊失真比 28 3.1.2 訊號雜訊比 28 3.1.3 無雜波干擾之動態範圍 28 3.1.4 解析度 28 3.1.5 動態範圍 29 3.2 量化器與量化誤差 30 3.2.1 一位元量化器 30 3.2.1 多位元量化器 32 3.2.2 量化誤差 36 3.3 超取樣 38 3.4 雜訊移頻 40 3.4.1 一階雜訊移頻 41 3.4.2 二階雜訊移頻 45 3.5 章節結論 48 第四章 電路元件設計 49 4.1 前言 49 4.2 開關 49 4.2.1 NMOS與PMOS開關 49 4.2.2 傳輸閘開關 51 4.2.3 靴帶式開關 51 4.3 交換電容式電路 54 4.3.1 非反向積分器 54 4.3.2 反向積分器 57 4.4運算放大器 59 4.1.1運算放大器設計需求 61 4.5共模準位電路 64 4.5.1推導 65 4.5.1探討 66 4.6量化器 67 4.7比較器 69 4.8偏壓電路 71 4.9電壓位準移位器 73 4.10二階低通濾波器 73 4.10.1 半橋 (Half-Bridge) 73 4.10.2 全橋 (Full-Bridge) 75 4.11非重疊時脈電路 76 4.12時脈產生器 77 4.13驅動電路 77 4.14章節結論 78 第五章 基於三角積分調變器之D類功率放大器設計與實現 79 5.1前言 79 5.2 基於三角積分調變器之D類功率放大器探討與構想 80 5.2.1 D類功率放大器之功率電晶體控制探討 80 5.2.2 D類功率放大器之功率電晶體控制構想 81 5.3二階三位元DSM對Class-D簡單控制方法原理 84 5.3.1 控制訊號原理與設計 85 5.3.2 控制訊號電路設計與HSPICE模擬 88 5.4二階三位元三角積分調變器之等效線性MATLAB模擬 93 5.4.1二階三位元三角積分調變器等效線性架構 93 5.4.2等效線性架構MATLAB模擬結果 94 5.5電路之非理想效應 96 5.5.1熱雜訊 96 5.5.2時脈抖動 98 5.5.3運算放大器之有限增益考量 99 5.5.4運算放大器之閉迴路附載電容考量 101 5.5.5運算放大器之迴轉率、有限單一增益頻寬與最小電流考量 103 5.6三角積分調變器之設計 107 5.6.1 運算放大器設計 107 5.6.2 二階三位元三角積分調變器模擬結果 109 5.7輸出級設計 111 5.8 回授設計 111 5.9整體電路實現與模擬 113 5.9.1.整體電路設計 113 5.9.2 整體電路模擬 116 5.11電路佈局 117 5.12封裝與磅線效應 120 5.13晶片量測 121 5.13.1輸入訊號與終端電路 122 5.13.2供應電壓元電路的產生―高電位 123 5.13.3供應電壓元電路的產生―低電位 124 5.13.4濾波槽電路 124 5.13.5量測考量 125 5.14章節結論 126 第六章 總結與未來展望 127 6.1 總結 127 6-2未來展望 127 參考文獻 129

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