過去數十年來，金氧半場效電晶體 (Metal-Oxide-Semiconductor FieldEffect Transistor, MOSFET)在半導體工程中扮演著相當重要的角色，但元件尺寸遵循著摩爾定律的法則微縮至今，亦遭遇到許多困難需要解決。穿隧型場效電晶體 (Tunnel Field Effect Transistor, TFET) 被視為其中一種相當有潛力能取代MOSFET 的元件，由於TFET 能夠擁有低於60 mV/dec 的次臨界擺幅，以及非常小的漏電流，這些特點有利於VD 的微縮，降低能源消耗的問題，因此適合應用在低功率的元件裡。但目前研究文獻均指出，TFET 最大的致命傷在於開狀態的電流值過低，大幅限制了TFET 的發展性。因此本研究利用半導體模擬工具 (Technology Computer Aided Design, TCAD)，設計出一個具有垂直穿隧機制的結構，並探討在n 型與p 型TFET 中，優化元件參數與使用異質接面的方式提升TFET 性能，最後將具有垂直穿隧與側向穿隧機制的結構進行整合。結果顯示擁有大面積的垂直穿隧機制的確能夠有效提升穿隧電流，使用矽鍺與矽所形成的異質接面亦能夠幫助穿隧效應的產生，最後將兩種穿隧機制整合在同一元件上的概念，結果也顯示能夠提升元件的整體開電流，幫助克服TFET 開電流值過小的問題。

Tunnel field effect transistor (TFET) has attracted attention for sub-60mV/decade subthreshold swing and very small OFF current (IOFF), and it serves as an attractive candidate for low-power applications. But one of the major engineering challenges of TFET is the boosting of its ION. A minimized subthreshold swing with a high on-current and low off-current is the key requirement for a TFET to be an ideal switching device. In this investigation, a novel vertical tunneling mechanism design to achieve more tunnel area of TFET is proposed to analyze the characteristic of ID-VG in TFET by two-dimensional(2D) Technology Computer Aided Design (TCAD). The analytic results show that vertical tunneling mechanism combined with silicon germanium (SiGe) heterojunction can be efficiently utilized to enhance the performance of TFET. Finally, we have demonstrated simple concepts to improve and optimize the contribution of vertical tunneling current in a combined vertical and lateral TFET. The results showed that the performance of TFET can be improved by the contribution from lateral tunneling.

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