Author: |
鄭怡建 Cheng, Yi-Chien |
---|---|
Thesis Title: |
C頻帶互補式金屬氧化物半導體功率放大器與線性化技術研究 Research on C-band CMOS Power Amplifiers and Linearization Techniques |
Advisor: |
蔡政翰
Tsai, Jen-Han |
Degree: |
碩士 Master |
Department: |
電機工程學系 Department of Electrical Engineering |
Thesis Publication Year: | 2017 |
Academic Year: | 105 |
Language: | 中文 |
Number of pages: | 203 |
Keywords (in Chinese): | C頻段 、功率放大器 、功率合成技術 、變壓器 、線性器 、互補式金屬氧化物半導體 |
Keywords (in English): | C-band, power amplifier, power combining techniques, transformer, linearizer, CMOS |
DOI URL: | https://doi.org/10.6345/NTNU202203058 |
Thesis Type: | Academic thesis/ dissertation |
Reference times: | Clicks: 79 Downloads: 3 |
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第一顆電路為使用變壓器功率合成技術之C頻段功率放大器,以變壓器功率合成技術完成放大器功率結合,並藉由阻抗轉換特性達成輸出與輸入之阻抗匹配。當操作頻率為5.3 GHz且VG1為0.85 V時,功率增益約16.48 dB,飽和輸出功率(Psat)約為27.69 dBm,1-dB增益壓縮點之輸出功率(OP1dB)約為22.53 dBm,最大功率附加效率(PAE)約為28.34 %。整體晶片佈局面積為1.17 mm × 0.655 mm。
第二顆電路為具內建線性器之C頻段功率放大器,線性器架構採用共閘極串級二極體組態。當操作頻率為5.3 GHz,且VG1為1 V線性器開啟時,功率增益約14.25 dB,飽和輸出功率(Psat)約為27.06 dBm,1-dB增益壓縮點之輸出功率(OP1dB)從22.48 dBm提升至26.24 dBm,最大功率附加效率(PAE)約為23.94 %,三階交互調變失真IMD3在輸出功率約為18 dBm以前皆可抑制在-40 dBc左右。整體晶片佈局面積為1.14 mm × 0.64 mm。
第三顆電路為具內建線性器之C頻段功率放大器,線性器架構採用疊階組態。當操作頻率為5.3 GHz ,且VG1為0.85 V線性器開啟時,功率增益約11.98 dB,飽和輸出功率(Psat)約為26.84 dBm,1-dB增益壓縮點之輸出功率(OP1dB)從 22.69 dBm提升至24.7 dBm,最大功率附加效率(PAE)約為22.22 %,而三階交互調變失真IMD3在輸出功率約為18.5 dBm以前皆可抑制在-40 dBc左右。整體晶片佈局面積為1.14 mm × 0.64 mm。
第四顆電路為具內建線性器之C頻段功率放大器,線性器架構採用共閘極串級電阻組態。當操作頻率為5.3 GHz ,且VG1為0.85 V線性器開啟時,功率增益約13.1 dB,飽和輸出功率(Psat)約為26.94 dBm,1-dB增益壓縮點之輸出功率(OP1dB)從20.95 dBm提升至23.81 dBm,最大功率附加效率(PAE)約為25.05 %,而三階交互調變失真IMD3在輸出功率約為18.5 dBm以前皆可抑制在-40 dBc左右。整體晶片佈局面積為1.14 mm × 0.64 mm。
The first circuit is power amplifier, operating at C-band, and using transformer combination technology to combine output power from two way amplifiers. And it can also convert characteristic impedance at both input and output. When the circuit operates at 5.3 GHz and VG1 is 0.85 V, the power gain is about 16.48 dB, and saturation output power (Psat) is about 22.34 dBm, 1 dB output power compression point (OP1dB) is about 22.53 dBm, and the maximum power-added efficency (PAE) is about 28.34%. The overall chip size is 1.17 mm × 0.655 mm.
Second circuit is power amplifier with built-in linearizer, operating at C-band, the frame of linearizer is using common gate cascade diode configuration. When the circuit with linearizer operates at 5.3 GHz, VG1 is 1V, the power gain is about 14.25 dB, saturation output power (Psat) is about 27.06 dBm, 1 dB output power compression point (OP1dB) increased from 22.48 dBm to 26.24 dBm, and the maximum power-added efficency (PAE) is about 23.94%, and third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 18 dBm. The overall chip size is 1.14 mm × 0.64 mm.
Third circuit is power amplifier with built-in linearizer, operating at C-band, the frame of linearizer is using cascode configuration. When the circuit with linearizer operates at 5.3 GHz, VG1 is 0.85 V, the power gain is about 11.98 dB, saturation output power (Psat) is about 26.84 dBm, 1 dB output power compression point (OP1dB) increased from 22.69 dBm to 24.7 dBm, and the maximum power-added efficency (PAE) is about 22.22%, and third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 18.5 dBm. The overall chip size is 1.14 mm × 0.64 mm.
Last circuit is power amplifier with built-in linearizer, operating at C-band, the frame of linearizer is using common gate cascade resistance configuration. When the circuit with linearizer operates at 5.3 GHz, VG1 is 0.85 V, the power gain is about 13.1 dB, saturation output power (Psat) is about 26.94 dBm, 1 dB output power compression point (OP1dB) increased from 20.95 dBm to 23.81 dBm, and the maximum power-added efficency (PAE) is about 25.05%, and third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 18.5 dBm. The overall chip size is 1.14 mm × 0.64 mm.
參考文獻
[1] National Instrument WLAN應用說明: Introduction to Wireless LAN Measurements From 802.11a to 802.11ac
[2] Tektronix datasheet: Tektronix wifi solutions 802.11 datasheet,2013
[3] National Instrument技術文件: Introduction to 802.11ax High-Efficiency Wireless,http://www.ni.com/white-paper/53150/en/,2016
[4] 2016是德科技電子量測論壇: A-2 Overview of Latest WiFi Technologies and Test Solution,2016
[5] P. Haldi, D. Chowdhury, and P. Reynaert, “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1054-1063, May 2008.
[6] C. S. Wu, C. H. Chang, H. C. Liu, T. Y. Ko, and H. C. Chiu, “High Linearity 5.2 GHz Power Amplifier MMIC using the Linearizer Circuit”, Microwave Conference 2008 China-Japan Joint, pp. 633-635, Sep. 2008.
[7] D. Gruner, and G. Boeck, “Fully integrated 5.6-6.4 GHz power amplifier using transformer combining,” Conferene on Ph. D. Research in Microelectronics and Electronics PRIME, 2009.
[8] T.-P. Wang, J.-H. Ke, and C.-Y. Chiang, “A high-Psat high-PAE ful-ly-integrated 5.8-GHz power amplifier in 0.18-µm CMOS,” in IEEE Electron Devices and Solid-State Circuits (EDSSC), pp. 1-2, Nov. 2011.
[9] C.-C. Kuo, Y.-W. Hsu, W.-C. Huang, H. Wang, and H.-C. Lu, “Performance Comparison of Flip-Chip-Assembled 5-GHz 0.18-μm CMOS Power Amplifiers on Different Packaging Substrates,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3, no. 12, pp. 2014-2021, Dec. 2013.
[10] J.-H. Tsai, and H.-W. Ou-Yang, “A 5-5.8 GHz Fully-Integrated CMOS PA for WLAN Applications,” 2014 IEEE Radio and Wireless Symposium (RWS), pp. 130 – 132, Jan. 2014.
[11] B. François, and P. Reynaert, “A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 5, pp. 1237-1250, May 2015.
[12] G. Gonzalez, Microwave Transistor Amplifier Analysis and Design, 2nd ed., Prentice Hall, 1997.
[13] B. Razavi, RF Microelectronics, 2nd ed., Prentice Hall, 2012.
[14] S. C. Cripps, RF POWER AMPLIFIERS FOR WIRELESS COMMUNICATIONS, 2nd ed., Artech House, 2006.
[15] D. M. Pozar, Microwave Engineering, 3rd ed., John Wiley & Sons Inc., 2004.
[16] J. Kim, Y. Yoon, H. Kim, K. H. An, W. Kim, H.-W. Kim, C.-H. Lee, and K. T. Kornegay, “A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1034-1048, May 2011.
[17] Y. Wang, and J.-S. Yuan, “An Integrated CMOS High Power Amplifier using Power Combining Technique,” 2012 Proceedings of IEEE, pp. 1-6, Mar 2012.
[18] J. Kim, W. Kim, H. Jeon, Y.-Y. Huang, Y. Yoon, H. Kim, C.-H. Lee, and K. T. Kornegay, “A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 599-614, Mar. 2012.
[19] J. Oh, B. Ku, and S. Hong, “A 77-GHz CMOS Power Amplifier With a Parallel Power Combiner Based on Transmission-Line Transformer,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 7, pp. 2662-2669, July 2013.
[20] C.-C. Kuo, Y.-H. Lin, H.-C. Lu, and H. Wangand, “A K-band Compact Fully Integrated Transformer Power Amplifier in 0.18-μm CMOS,” 2013 Asia-Pacific Microwave Conference Proceedings (APMC), pp. 597-599, Nov. 2013.
[21] J.-F. Yeh, Y.-F. Hsiao, J.-H. Tsai, T.-W. Huang, “MMW Ultra-Compact -Way Transformer PAs Using Bowtie-Radial Architecture in 65-nm CMOS,” IEEE Microwave and Wireless Components Letters, vol. 25, no. 7, pp. 460-462, July 2015.
[22] B. Leite, E. Kerhervé, and D. Belot, “Design of 28 nm CMOS integrated transformers for a 60 GHz power amplifier,” 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1-6, Aug 2015.
[23] J.-H. Cheng, S.-J. Luo, W.-J. Lin, J.-H. Tsai, and T.-W. Huang, “A 24-GHz Transformer-Based Stacked-FET Power Amplifier in 90-nm CMOS Technology,” 2015 Asia-Pacific Microwave Conference (APMC), vol. 3, pp. 1-3, Dec. 2015.
[24] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Distributed Active Transformer—A New Power-Combining and Impedance-Transformation Technique,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 316-331, Jan. 2002.
[25] Y. Han, and D. J. Perreault, “Analysis and Design of High Efficiency Matching Networks,” IEEE Transactions on Power Electronics, vol. 21, no. 5, pp. 1484-1491, Sept. 2006.
[26] A.M. Niknejad, electromagnetics for high-speed analog and digital communication circuits, Cambridge University Press, Mar. 2007.
[27] A. M. Niknejad, D. Chowdhury, and J. Chen, “Design of CMOS Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 6, pp. 1784-1796, Jun. 2012.
[28] J.-H. Tsai, H.-Y. Chang, P.-S. Wu, Y.-L. Lee, T.-W. Huang, and H. Wang, “Design and Analysis of a 44-GHz MMIC Low-Loss Built-In Linearizer for High-Linearity Medium Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 6, pp. 2487-2496, Jun. 2006.
[29] K.-Y. Kao, Y.-C. Hsu, K.-W. Chen, and K.-Y. Lin, “Phase-Delay Cold-0FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 12, pp. 4505-4519, Dec. 2013.
[30] J.-F. Yeh, J.-H. Cheng, J.-H. Tsai, and T.-W. Huang, “A 57-66 GHz power amplifier with a linearization technique in 65-nm CMOS technology,” Microwave Conference (EuMC), pp. 1253-1256, Oct. 2014.
[31] T.-Y. Huang, Y.-H. Lin, and H. Wang, “A K-Band Adaptive-Bias Power Amplifier with Enhanced Linearizer Using 0.18-um CMOS Process,” 2015 IEEE MTT-S International Microwave Symposium, pp. 1-3, May. 2015.